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73K324L Schematic ( PDF Datasheet ) - ETC

Teilenummer 73K324L
Beschreibung CCITT V.22bis/ V.22/ V.21/ V.23/ Bell 212A Single-Chip Modem
Hersteller ETC
Logo ETC Logo 




Gesamt 30 Seiten
73K324L Datasheet, Funktion
73K324L
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
Single-Chip Modem
DESCRIPTION
The 73K324L is a highly integrated single-chip
modem IC which provides the functions needed to
design a Quad-mode CCITT and Bell 212A
compatible modem capable of operation over dial-up
lines. The 73K324L adds V.23 capability to the
CCITT modes of TDK Semiconductor Corporation's
73K224 one-chip modem, allowing a one-chip
implementation in designs intended for European
markets which require this added Modulation mode.
The 73K324L offers excellent performance and a
high level of functional integration in a single IC. The
device supports V.22bis, V.22, Bell 212A, V.21, and
V.23 operating modes, allowing both synchronous
and asynchronous operation as defined by the
appropriate standard.
The 73K324L is designed to appear to the Systems
Engineer as a microprocessor peripheral, and will
easily interface with popular one-chip
microcontrollers (80C51 typical) for control of
modem functions through its 8-bit multiplexed
address/data bus. A serial control bus is available
for applications not requiring a parallel interface. An
optional package with only the serial control bus is
also available. Data communications occurs through
a separate serial port.
(continued)
FEATURES
April 2000
One chip Multi-mode CCITT V.22bis, V.22, V.21,
V.23 and Bell 212A compatible modem data pump
FSK (75, 300, 1200 bit/s), DPSK (600, 1200 bit/s),
or QAM (2400 bit/s) encoding
Pin and software compatible with other
TDK Semiconductor Corporation K-Series family
one-chip modems
Interfaces directly with standard
microprocessors (8048, 80C51 typical)
Serial and parallel microprocessor bus for
control
Selectable asynch/synch with internal
buffer/debuffer and scrambler/descrambler
functions
All synchronous (internal, external, slave) and
Asynchronous Operating modes
Adaptive equalization for optimum performance
over all lines
Programmable transmit attenuation (16 dB, 1 dB
steps), and selectable receive boost (+18 dB)
Call progress, carrier, answer tone, unscrambled
mark, S1, and signal quality monitors
DTMF, answer, calling, SCT and guard tone
generators
Test modes available: ALB, DL, RDL; Mark, Space
and Alternating bit pattern generators
CMOS technology for low power consumption
(100 MW @ 5 V) with power-down mode
(15 mW @ 5V)
4-wire full duplex operation in all modes
BLOCK DIAGRAM
8 - BIT
mP
BUS
I/F
TXD
RXD
SERIAL
I/F
BUFFER
FSK
MODULATOR
DTMF,
ANSWER,
GUARD &
CALLING
TONE
GENERATOR
SCRAMBLER
DIBIT/
QUADBIT
ENCODER
FIR
PULSE
SHAPER
QAM/
DPSK
MODULATOR
+
EQUALIZER
FILTER
+
ATTEN
FILTER
TXA
DEBUFFER
DE-
SCRAMBLER
DIBIT/
QUADBIT
DECODER
DIGITAL
SIGNAL
PROCESSOR
RECEIVE
FUNCTIONS
FILTER
A/D
AGC
EQUALIZER
FIXED
DEMOD
6 dB
GAIN
BOOST
FILTER
6 dB
GAIN BOOST
FILTER
RXA
TONE DETECTION






73K324L Datasheet, Funktion
73K324L
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
Single-Chip Modem
REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for
control and status monitoring. The registers are
accessed in read or write operations by addressing
the A0, A1 and A2 address lines in Serial mode, or
the AD0, AD1 and AD2 lines in Parallel mode. The
address lines are latched by ALE. Register CR0
controls the method by which data is transferred
over the phone line. CR1 controls the interface
between the microprocessor and the 73K324L
internal state. DR is a detect register which provides
an indication of monitored modem status conditions.
TR, the tone control register, controls the DTMF
generator, answer, guard tones, SCT, calling tone,
and RXD output gate used in the modem initial
connect sequence. CR2 is the primary DSP control
interface and CR3 controls transmit attenuation and
receive gain adjustments. All registers are read/write
except for DR and ID which are read only. Register
control and status bits are identified below:
REGISTER BIT SUMMARY
REGISTER
ADDRESS
AD - A0
CONTROL
REGISTER
0
CR0
000
CONTROL
REGISTER
1
CR1
001
DETECT
REGISTER
DR
010
TONE
CONTROL
REGISTER
TR
CONTROL
REGISTER
2
CR2
CONTROL
REGISTER
3
CR3
011
100
101
DATA BIT NUMBER
D7 D6 D5 D4 D3
MODULATION
OPTION
TRANSMIT
PATTERN
1
MODULATION
TYPE
1
TRANSMIT
PATTERN
0
MODULATION
TYPE
0
ENABLE
DETECT
INTERRUPT
TRANSMIT
MODE
2
BYPASS
SCRAMBLER/
ADD PH. EQ.
(V.23)
TRANSMIT
MODE
1
CLK
CONTROL
RECEIVE
LEVEL
RXD
OUTPUT
CONTROL
PATTERN
S1 DET
TRANSMIT
GUARD TONE/
SCT/CALLING
TONE
RECEIVE
DATA
TRANSMIT
ANSWER
TONE
UNSCR.
MARK
DETECT
TRANSMIT
DTMF
CARRIER
DETECT
DTMF3
0
SPECIAL
REGISTER
CALL
INITIALIZE
TRANSMIT
S1
16 WAY
ACCESS
TXDALT
TRISTATE
TX/RXCLK
0
RECEIVE
GAIN
TRANSMIT
ATTEN.
BOOST
3
SPECIAL
REGISTER
SR
101
0
TX BAUD
RX UNSCR.
0
CLOCK
DATA
TXD
SOURCE
ID
REGISTER
ID 110
1
1
10
X
D2
TRANSMIT
MODE
0
RESET
SPECIAL
TONE
DETECT
DTMF2/
4 WIRE FDX
RESET
DSP
TRANSMIT
ATTEN.
2
SQ
SELECT 1
X
D1
TRANSMIT
ENABLE
D0
ANSWER/
ORIGINATE
TEST
MODE
1
TEST
MODE
0
CALL
PROGRESS
DETECT
SIGNAL
QUALITY
DTMF1/
OVERSPEED
DTMF0/GUARD/
ANSWER/
CALLING/SCT
TRAIN
INHIBIT
TRANSMIT
ATTEN.
1
SQ
SELECT 0
EQUALIZER
ENABLE
TRANSMIT
ATTEN.
0
0
XX
NOTE: When a register containing reserved control bits is written into, the reserved bits must be programmed as
0's.
X = Undefined, mask in software.
6

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73K324L pdf, datenblatt
73K324L
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
Single-Chip Modem
TONE REGISTER
D7 D6
D5 D4 D3 D2 D1
D0
TR
RXD
TRANSMIT TRANSMIT TRANSMIT DTMF 3 DTMF 2/ DTMF 1/
DTMF 0/
011 OUTPUT
GUARD/
ANSWER
DTMF
WIRE
OVER-
G.T./ANSW./
CONTR. CALLING/SCT
TONE
FDX
SPEED CALLING/SCT
TONE
TONE/SEL
BIT NO.
D0, D4, D5, D6
D1
D2
NAME
DTMF
0/Guard
Tone/Answer
Tone/Calling/
SCT Tone/
Transmit
Select
DTMF 1/
Overspeed
DTMF 2/
4 WIRE
FDX
CONDITION
DESCRIPTION
D6 D5 D4 D0 D0 interacts with bits D6, D5, D4, and CR0 as shown.
X X 1 X Transmit DTMF tones (overides all other functions).
1 0 0 0 Select 1800 Hz guard tone if in V.22bis or V.22 and
Answer mode in CR0.
1 0 0 1 Select 550 Hz guard tone if in V.22bis or V.22 and
Answer mode in CR0.
Note: Bit D0 also selects the answer tone detected in Originate mode, see
Detect Register Special Tone Detect (bit D2) for details.
1 0 0 0 1300 Hz calling tone will be transmitted if V.22, V.22bis or
V.23 Originate mode is selected in CR0.
X 1 0 0 Transmit 2225 Hz Answer Tone. Must be in DPSK
Answer mode.
X 1 0 1 Transmit 2100 Hz Answer Tone. Must be in DPSK
Answer mode.
1 0 0 1 900 Hz SCT (soft carrier turnoff) tone transmitted in V.23
75 bit/s Receive mode. (CR0 bit D0 = 1).
D4 D1
D1 interacts with D4 as shown.
00
Asynchronous QAM/DPSK +1% -2.5%. (Normal).
01
Asynchronous QAM/DPSK, 2400, 1200 or 600 bit/s
+2.3% -2.5%. (Extended overspeed).
D4 D2
00
Selects 2-wire full-duplex or half-duplex.
01
D2 selects 4 wire full duplex in the Modulation mode
selected. The receive path corresponds to the ANS/ORIG
bit CR0 D0 in terms of high or low band selection. The
transmitter is in the same band as the receiver, but does
not have magnitude filtering or equalization on its signal
as in the receive path.
NOTE: DTMF0 - DTMF2 should be set to an appropriate state after DTMF dialing to avoid unintended
operation.
12

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