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73K224BL-IH Schematic ( PDF Datasheet ) - ETC

Teilenummer 73K224BL-IH
Beschreibung Single-Chip Modem w/ Integrated Hybrid
Hersteller ETC
Logo ETC Logo 




Gesamt 30 Seiten
73K224BL-IH Datasheet, Funktion
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
DESCRIPTION
The 73K224BL is a highly integrated single-chip
modem IC which provides the functions needed to
construct a V.22bis compatible modem, capable of
2400 bit/s full-duplex operation over dial-up lines.
The 73K224BL is an enhancement of the 73K224L
single-chip modem which adds the hybrid hook
switch control, and driver to the 73K224L. The
73K224BL integrates analog, digital, and switched-
capacitor array functions on a single chip, offering
excellent performance and a high level of functional
integration in a 32-Lead PLCC and 44-Lead TQFP
package.
The 73K224BL operates from a single +5 V supply
for low power consumption.
The 73K224BL is designed to appear to the systems
designer as a microprocessor peripheral, and will
easily interface with popular single-chip micro-
processors (80C51 typical) for control of modem
functions through its 8-bit multiplexed address/data
bus or via an optional serial control bus. An ALE
control simplifies address demultiplexing. Data
communications normally occur through a separate
serial port.
(continued)
FEATURES
April 2000
Includes features of 73K224L single-chip
modem
On chip 2-wire/4-wire hybrid driver and off
hook relay buffer driver
One-chip multi-mode V.22bis/V.22/V.21 and
Bell 212A/103 compatible modem data pump
FSK (300 bit/s), DPSK (600, 1200 bit/s), or
QAM (2400 bit/s) encoding
Software compatible with other TDK
Semiconductor K-Series one-chip modems
Interfaces directly with standard micro-
processors (80C51 typical)
Parallel or serial bus for control
Selectable internal buffer/debuffer and
scrambler/descrambler functions
All asynchronous and synchronous
operating modes (internal, external, slave)
(continued)
BLOCK DIAGRAM
OH
8-BIT
µP
BUS
INTERFACE
TXD
RXD
SERIAL
INTERFACE
FSK
MODULATOR
DTMF,
ANSWER,
GUARD &
CALLING
TONE
GENERATOR
BUFFER
SCRAMBLER
DI-BIT/
QUAD-BIT
ENCODER
FIR
PULSE
SHAPER
QAM/
DPSK
MODULATOR
EQUALIZER
FILTER
FILTER
ATTENUATOR
DEBUFFER
DESCRAMBLER
DI-BIT/
QUAD-BIT
DECODER
DIGITAL
SIGNAL
PROCESSOR
RECEIVE
FUNCTIONS
TONE
DETECTION
FILTER
A/D
EQUALIZER
FIXED
DEMODULATOR
FILTER
AGC
2W/4W
HYBRID
GAIN
BOOST
FILTER
TXA1
TXA2
RXA






73K224BL-IH Datasheet, Funktion
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
PARALLEL MICROPROCESSOR INTERFACE (continued)
NAME
WR
PIN TYPE DESCRIPTION
14 I WRITE: A low on this informs the 73K224BL that data is
available on AD0-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low.
SERIAL MICROPROCESSOR CONTROL INTERFACE MODE
NAME
AD0-AD2
DATA (AD7)
RD
WR
PIN TYPE DESCRIPTION
5-7 I REGISTER ADDRESS SELECTION: These lines carry
register addresses and should be valid during any read or
write operation.
12 I/O SERIAL CONTROL DATA: Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.
15 I READ: A low on this input informs the 73K224BL that data or
status information is being read by the processor. The falling
edge of the RD signal will initiate a read from the addressed
register. The RD signal must continue for eight falling edges
of EXCLK in order to read all eight bits of the referenced
register. Read data is provided LSB first. Data will not be
output unless the RD signal is active.
14 I WRITE: A low on this input informs the 73K224BL that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on the
DATA pin for eight consecutive falling edges of EXCLK and
then to pulse WR low. Data is written on the rising edge of
WR.
NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes
DATA and AD0, AD1 and AD2 become the register address.
6

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73K224BL-IH pdf, datenblatt
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
CONTROL REGISTER 1 (continued)
CR1
ADDR
001
BIT
D4
D7 D6
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
NAME
Bypass
Scrambler
D5
ENABLE
DETECT
INTERRUPT
CONDITION
0
1
D5 Enable Detect 0
Interrupt
1
D6, D7
Transmit
Pattern
D7 D6
00
01
10
11
D4
BYPASS
SCRAMBLER
D3
CLOCK
CONTROL
D2
RESET
D1
TEST
MODE 1
D0
TEST
MODE 0
DESCRIPTION
Selects normal operation. DPSK and QAM data is
passed through scrambler.
Selects Scrambler bypass. Bypass DPSK and QAM
data is route around scrambler in the transmit path.
Disables interrupt at INT pin. All interrupts are normally
disabled in power-down mode.
Enables INT output. An interrupt will be generated with a
change in status of DR bits D1- D4 and D6. The answer
tone and call progress detect interrupts are masked
when the TX enable bit is set. Carrier detect is masked
when TXDTMF is activated. All interrupts will be
disabled if the device is in power-down mode.
Selects normal data transmission as controlled by the
state of the TXDpin.
Selects an alternating mar/space transmit pattern for
modem testing and handshaking. Also used for S1
pattern generation (see CR2 bit D4).
Selects a constant mark transmit pattern.
Selects a constant space transmit pattern.
DETECT REGISTER
DR
ADDR
010
BIT
D0
D1
D7 D6 D5 D4 D3 D2 D1 D0
RECEIVE
LEVEL
INDICATOR
S1
PATTERN
DETECT
RECEIVE
DATA
UNSCR.
MARK
DETECT
CARR.
DETECT
ANSWER
TONES
DETECT
CALL
PROG.
DETECT
SIGNAL
QUALITY
INDICATOR
NAME
CONDITION DESCRIPTION
Signal Quality
0 Indicates normal received signal.
Indicator
1 Indicates low received signal quality (above average
error rate). Interacts with Special Register bits D2, D1.
Call Progress
0 No call progress tone detected.
Detect
1 Indicates presence of call progress tones. The call
progress detection circuitry is activated by energy in the
normal 350 to 620 Hz call progress bandwidth.
12

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