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7343 Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer 7343
Beschreibung DIGITALLY CONTROLLED AUDIO PROCESSOR
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 14 Seiten
7343 Datasheet, Funktion
® TDA7343
DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
- TWO STEREO AND ONE MONO INPUTS
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
FULLY PROGRAMMABLE LOUDNESS
FUNCTION
VOLUME CONTROL IN 0.3dB STEPS IN-
CLUDING GAIN UP TO 20dB
ZERO CROSSING MUTE AND DIRECT
MUTE
SOFT MUTE CONTROLLED BY SOFTWARE
OR HARDWARE PIN
BASS AND TREBLE CONTROL
FOUR SPEAKER ATTENUATORS
- FOUR INDEPENDENT SPEAKERS
CONTROL IN 1.25dB STEPS FOR
BALANCE AND FADER FACILITIES
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I2 CBUS
DESCRIPTION
The TDA7343 is an upgrade of the TDA7313
audioprocessor.
Thanks to the used BIPOLAR/CMOS technology,
very low distortion, low noise and DC-stepping
are obtained.
Due to a highly linear signal processing, using
DIP28
SO28
ORDERING NUMBER: TDA7343 (DIP28)
TDA7343D (SO28)
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained Several new features like
softmute, zero-crossing mute and pause detector
are implemented.
The Soft Mute function can be activated in two
ways:
1 Via serial bus (bit D0, Mute Byte)
2 Directly on pin 22 through an I/O line of the
microcontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
November 1999
1/14






7343 Datasheet, Funktion
TDA7343
I2C BUS INTERFACE
Data transmission from microprocessor to the
TDA7343 and viceversa takes place thru the 2
wires I2C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
Figure 3: Data Validity on the I2CBUS
knowledge bit. The MSB is transferred first.
Acknowledge
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the µP can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 4: Timing Diagram of I2CBUS
Figure 5: Acknowledge on the I2CBUS
6/14

6 Page









7343 pdf, datenblatt
TDA7343
DIM.
MIN.
mm
TYP. MAX.
MIN.
inch
TYP. MAX.
A 2.65 0.104
a1 0.1
0.3 0.004
0.012
b 0.35
0.49 0.014
0.019
b1 0.23
0.32 0.009
0.013
C 0.5
0.020
c1 45° (typ.)
D 17.7
18.1 0.697
0.713
E 10
10.65 0.394
0.419
e 1.27
0.050
e3 16.51
0.65
F 7.4
7.6 0.291
0.299
L 0.4
1.27 0.016
0.050
S 8 ° (max.)
OUTLINE AND
MECHANICAL DATA
SO28
12/14

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