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74ACT109 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74ACT109
Beschreibung Dual JK Positive Edge-Triggered Flip-Flop
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 12 Seiten
74ACT109 Datasheet, Funktion
74AC109, 74ACT109
Dual JK Positive Edge-Triggered Flip-Flop
March 2007
tm
Features
ICC reduced by 50%
Outputs source/sink 24mA
ACT109 has TTL-compatible inputs
General Description
The AC/ACT109 consists of two high-speed completely
independent transition clocked JK flip-flops. The clocking
operation is independent of rise and fall times of the
clock waveform. The JK design allows operation as a
D-Type flip-flop (refer to AC/ACT74 data sheet) by
connecting the J and K inputs together.
Asynchronous Inputs:
– LOW input to SD (Set) sets Q to HIGH level
– LOW input to CD (Clear) sets Q to LOW level
– Clear and Set are independent of clock
– Simultaneous LOW on CD and SD makes both
Q and Q HIGH
Ordering Information
Order
Number
74AC109SC
74AC109SJ
74AC109MTC
Package
Number
M16A
M16D
MTC16
74ACT109SC
74AC109MTC
M16A
MTC16
74ACT109PC
N16E
Package Description
www.DataSheet4U.com
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Descriptions
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
www.fairchildsemi.com






74ACT109 Datasheet, Funktion
AC Electrical Characteristics for AC
Symbol
Parameter
fMAX Maximum Clock Frequency
tPLH Propagation Delay,
CPn to Qn or Qn
tPHL Propagation Delay,
CPn to Qn or Qn
tPLH Propagation Delay,
CDn or SDn to Qn or Qn
tPHL Propagation Delay,
CDn or SDn to Qn or Qn
VCC (V)(6)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
Min. Typ. Max. Min.
Max.
125 150
100
150 175
125
4.0 8.0 13.5
3.5
16.0
2.5 6.0 10.0
2.0
10.5
3.0 8.0 14.0
3.0
14.5
2.0 6.0 10.0
1.5
10.5
3.0 8.0 12.0
2.5
13.0
2.5 6.0 9.0
2.0
10.0
3.0 10.0 12.0
3.0
13.5
2.0 7.5 9.5
2.0
10.5
Units
MHz
ns
ns
ns
ns
Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements for AC
Symbol
Parameter
tS Setup Time, HIGH or LOW,
Jn or Kn to CPn
tH Hold Time, HIGH or LOW,
Jn or Kn to CPn
tW Pulse Width, CDn or SDn
tREC
Recovery Time,
CDn or SDn to CPn
VCC (V)(7)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
TA = +25°C, TA = –40°C to +85°C,
CL = 50pF
CL = 50 pF
Typ.
Guaranteed Minimum
3.5 6.5
7.5
2.0 4.5
5.0
–1.5 0
0
–0.5 0.5
0.5
2.0 7.0
7.5
2.0 4.5
5.0
–2.5 0
0
–1.5 0
0
Units
ns
ns
ns
ns
Note:
7. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
6
www.fairchildsemi.com

6 Page









74ACT109 pdf, datenblatt
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The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an
exhaustive list of all such trademarks.
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status
Advance Information
Formative or In Design
Preliminary
First Production
No Identification Needed Full Production
Obsolete
Not In Production
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
12
www.fairchildsemi.com

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