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74ACQ657 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74ACQ657
Beschreibung Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 10 Seiten
74ACQ657 Datasheet, Funktion
January 1990
Revised September 2000
74ACQ646 74ACTQ646
Quiet SeriesOctal Transceiver/Register
with 3-STATE Outputs
General Description
The ACQ/ACTQ646 consist of registered bus transceiver
circuits, with outputs, D-type flip-flops, and control circuitry
providing multiplexed transmission of data directly from the
input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on
the LOW-to-HIGH transition of the appropriate clock pin
(CPAB or CPBA). The four fundamental handling functions
available are illustrated in Figure 1, Figure 2, Figure 3 and
Figure 4.
The ACQ/ACTQ utilizes Fairchild Quiet Seriestechnol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Seriesfea-
tures GTOoutput control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Independent registers for A and B busses
s Multiplexed real-time and stored data transfers
s 300 mil slim dual-in-line package
s Outputs source/sink 24 mA
s Faster prop delays than the standard AC/ACT646
Ordering Code:
Order Number Package Number
Package Description
74ACQ646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ464ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ464ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A0A7
B0B7
CPAB, CPBA
SAB, SBA
G
DIR
Descriptions
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
FACT, Quiet Series, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation
© 2000 Fairchild Semiconductor Corporation DS010635
www.fairchildsemi.com






74ACQ657 Datasheet, Funktion
AC Electrical Characteristics for ACQ
VCC
TA = +25°C
TA = −40°C to +85°C
Symbol
Parameter
(V) CL = 50 pF
CL = 50 pF
Units
(Note 14)
Min
Typ
Max
Min
Max
tPLH Propagation Delay
Bus to Bus
3.3 3.5 9.0 12.0 3.5 13.0
5.0 2.5 6.5 9.0 2.5 9.5
ns
tPHL Propagation Delay
Bus to Bus
3.3 3.5 9.0 12.0 3.5 13.0
5.0 2.5 6.5 9.0 2.5 9.5
ns
tPLH Propagation Delay
Clock to Bus
3.3
3.5
10.0
13.0
3.5
14.0
5.0 2.5 7.0 9.5 2.5 10.5
ns
tPHL Propagation Delay
Clock to Bus
3.3
3.5
10.0
13.0
3.5
14.0
5.0 2.5 7.0 9.5 2.5 10.5
ns
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
tOS
Propagation Delay
SBA or SAB to An or Bn
(w/An or Bn HIGH or LOW)
Propagation Delay
SBA or SAB to An or Bn
(w/An or Bn HIGH or LOW)
Enable Time
G to An or Bn
Enable Time
G to An or Bn
Disable Time
G to An or Bn
Disable Time
G to An or Bn
Enable Time
DIR to An or Bn
Enable Time
DIR to An or Bn
Disable Time
DIR to An or Bn
Disable Time
DIR to An or Bn
Output to Output Skew (Note 15)
3.3 3.5 9.5 12.5 3.5 13.5
5.0 2.5 6.5 9.0 2.5 10.0
3.3 3.5 9.5 12.5 3.5 13.5
5.0 2.5 6.5 9.0 2.5 10.0
3.3
3.5
10.5
14.5
3.5
15.5
5.0 2.5 8.0 10.5 2.5 11.5
3.3
3.5
10.5
14.5
3.5
15.5
5.0 2.5 8.0 10.5 2.5 11.5
3.3 2.5 8.0 11.0 2.5 12.0
5.0 1.5 5.0 7.5 1.5 8.0
3.3 2.5 8.0 11.0 2.5 12.0
5.0 1.5 5.0 7.5 1.5 8.0
3.3 4.5 11.0 15.5 4.5 17.0
5.0 3.0 8.5 11.0 3.0 11.5
3.3 4.5 11.0 15.5 4.5 17.0
5.0 3.0 8.5 11.0 3.0 11.5
3.3 1.5 8.0 11.0 1.5 12.0
5.0 1.0 5.0 7.5 1.0 8.0
3.3 1.5 8.0 11.0 1.5 12.0
5.0 1.0 5.0 7.5 1.0 8.0
3.3 1.0 1.5 1.5
5.0 0.5 1.0 1.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 14: Voltage Range 3.3 is 3.3V ± 0.3V.
Voltage Range 5.0 is 5.0V ± 0.5V
Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by
design. Not tested.
AC Operating Requirements for ACQ
Symbol
Parameter
tS Setup Time, HIGH or LOW
Bus to Clock
tH Hold Time, HIGH or LOW
Bus to Clock
tW Clock Pulse Width
HIGH or LOW
Note 16: Voltage Range 5.0 is 5.0V ± 0.5V
Voltage Range 3.3 is 3.3V ± 0.3V
VCC
(Note 16)
3.3
5.0
3.3
5.0
3.3
5.0
TA = +25°C
TA = −40°C to +85°C
Typ Guaranteed Minimum
3.0 3.0
3.0 3.0
1.5 1.5
1.5 1.5
4.0 4.0
4.0 4.0
Units
ns
ns
ns
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