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PDF 74ABT16952 Data sheet ( Hoja de datos )
| Número de pieza | 74ABT16952 | |
| Descripción | 16-Bit Registered Transceiver with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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November 1993
Revised January 1999
74ABT16952
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ABT16952 is a 16-bit registered transceiver. Two 8-bit
back to back registers store data flowing in both directions
between two bidirectional buses. Separate clock, clock
enable and 3-STATE output enable signals are provided for
each register. The output pins are guaranteed to source 32
mA and to sink 64 mA.
Features
s Separate clock, clock enable and 3-STATE output
enable provided for each register
s A and B output sink capability of 64 mA source capability
of 32 mA
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT16952CSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16952CMTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.
Pin Descriptions
Connection Diagram
Pin Names
A0–A15
B0–B15
CPABn, CPBAn
CEAn, CEBn
OEABn, OEBAn
Description
Data Register A Inputs/
B-Register 3-STATE Outputs
Data Register B Inputs/
A-Register 3-STATE Outputs
Clock Pulse Inputs
Clock Enable
Output Enable Inputs
Output Control
Pin Assignment for SSOP
OE Internal Output
Q
Function
HX
Z Disable Outputs
LL
L Enable Outputs
LH
H
Register Function Table
(Applies to A or B Register)
Inputs
Internal
D CP CE
Q
Function
XX
L
H
H NC Hold Data
L L Load Data
LH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
= LOW-to-HIGH Transition
NC = No Change
© 1999 Fairchild Semiconductor Corporation DS011647.prf
www.fairchildsemi.com
1 page  
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. Test Input Signal Levels
Amplitude Rep. Rate
tW
3.0V
1 MHz 500 ns
tr
2.5 ns
tf
2.5 ns
FIGURE 3. Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74ABT16952.PDF ] | |
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