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74ABT16245 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74ABT16245
Beschreibung 16-Bit Transceiver with 3-STATE Outputs
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 8 Seiten
74ABT16245 Datasheet, Funktion
April 1992
Revised May 2005
74ABT16245
16-Bit Transceiver with 3-STATE Outputs
General Description
The ABT16245 contains sixteen non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. Each
byte has separate control inputs which can be shorted
together for full 16-bit operation. The T/R inputs determine
the direction of data flow through the device. The OE inputs
disable both the A and B ports by placing them in a high
impedance state.
Features
s Bidirectional non-inverting buffers
s Separate control logic for each byte
s 16-bit version of the ABT245
s A and B output sink capability of 64 mA, source
capability of 32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and
250 pF loads
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Non-destructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT16245CSSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ABT16245CMTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OEn
T/Rn
A0A15
B0B15
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs/Outputs
Side B Inputs/Outputs
© 2005 Fairchild Semiconductor Corporation DS010986
www.fairchildsemi.com






74ABT16245 Datasheet, Funktion
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. Input Pulse Requirements
Amplitude Rep. Rate
tW
tr
tf
3.0V
1 MHz 500 ns 2.5 ns 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 6. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
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