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74ALVC16841 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74ALVC16841
Beschreibung Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 6 Seiten
74ALVC16841 Datasheet, Funktion
November 2001
Revised November 2001
74ALVC16841
Low Voltage 20-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16841 contains twenty non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The 74ALVC16841 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74ALVC16841 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I 1.65V–3.6V VCC supply operation
I 3.6V tolerant inputs and outputs
I tPD (Dn to On)
3.5 ns max for 3.0V to 3.6V VCC
3.9 ns max for 2.3V to 2.7V VCC
6.8 ns max for 1.65V to 1.95V VCC
I Power-off high impedance inputs and outputs
I Supports live insertion and withdrawal (Note 1)
I Uses patented noise/EMI reduction circuitry
I Latchup conforms to JEDEC JED78
I ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74ALVC16841MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
LEn
D0D19
O0O19
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation DS500690
www.fairchildsemi.com






74ALVC16841 Datasheet, Funktion
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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