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PDF 74ALVC162244T Data sheet ( Hoja de datos )

Número de pieza 74ALVC162244T
Descripción Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistor in Outputs
Fabricantes Fairchild Semiconductor 
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November 2001
Revised November 2001
74ALVC162244
Low Voltage 16-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26Series Resistor in Outputs
General Description
The ALVC162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74ALVC162244 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V. The
74ALVC162244 is also designed with 26series resistors
in the outputs. This design reduces line noise in applica-
tions such as memory address drivers, clock drivers, and
bus transceivers/transmitters.
The 74ALVC162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26series resistors in outputs
s tPD
3.8 ns max for 3.0V to 3.6V VCC
4.3 ns max for 2.3V to 2.7V VCC
7.6 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74ALVC162244GX
(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74ALVC162244T
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation DS500696
www.fairchildsemi.com

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74ALVC162244T pdf
AC Electrical Characteristics
Symbol
Parameter
tPHL, tPLH
tPZL, tPZH
tPLZ, tPHZ
Propagation Delay
Output Enable Time
Output Disable Time
Capacitance
TA = −40°C to +85°C, RL = 500
CL = 50 pF
CL = 30 pF
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5V ± 0.2V VCC = 1.8V ± 0.15V
Min Max Min Max Min Max Min Max
1.3 3.8 1.5 4.3 1.0 3.8 1.5 7.6
1.3 4.3 1.5 5.6 1.0 5.1 1.5 9.8
1.3 4.1 1.5 4.5 1.0 4.0 1.5 7.2
Symbol
Parameter
Conditions
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Outputs Enabled
VI = 0V or VCC
VI = 0V or VCC
f = 10 MHz, CL = 50 pF
TA = +25°C
VCC Typical
3.3 6
3.3 7
3.3 20
2.5 20
Units
ns
ns
ns
Units
pF
pF
pF
5 www.fairchildsemi.com

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