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74ACTQ543SPC Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74ACTQ543SPC
Beschreibung Quiet Series Octal Registered Transceiver with 3-STATE Outputs
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 9 Seiten
74ACTQ543SPC Datasheet, Funktion
www.DataSheet4U.com
January 1990
Revised August 2000
74ACQ54374ACTQ543
Quiet SeriesOctal Registered Transceiver
with 3-STATE Outputs
General Description
The ACQ/ACTQ543 is a non-inverting octal transceiver
containing two sets of D-type registers for temporary stor-
age of data flowing in either direction. Separate Latch
Enable and Output Enable inputs are provided for each
register to permit independent input and output control in
either direction of data flow.
The ACQ/ACTQ utilizes Fairchild Quiet Seriestechnol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance FACT Quiet Seriesfea-
tures GTOoutput control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s 8-bit octal latched transceiver
s Separate controls for data flow in each direction
s Back-to-back registers for storage
s Outputs source/sink 24 mA
s 300 mil slim PDIP/SOIC
Ordering Code:
Order Number Package Number
Package Description
74ACQ543SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ543SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ543SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ543QSC
MQA24
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
74ACTQ543SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code.
Connection Diagram
Pin Descriptions
Pin Names
Description
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A0A7
B0B7
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
FACT, Quiet Series, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010154
www.fairchildsemi.com






74ACTQ543SPC Datasheet, Funktion
AC Electrical Characteristics for ACTQ
VCC
TA = +25°C
TA = −40°C to +85°C
Symbol
Parameter
(V) CL = 50 pF
CL = 50 pF
Units
(Note 16)
Min
Typ
Max
Min
Max
tPLH Propagation Delay
tPHL Transparent Mode
An to Bn or Bn to An
tPLH Propagation Delay
tPHL
LEBA, LEAB
to An, Bn
tPZH Output Enable Time
tPZL OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
tPHZ
Output Disable Time
tPLZ OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
tOSHL
Output to Output
tOSLH
Skew (Note 17)
Note 16: Voltage Range 5.0 is 5.0V ± 0.5V
5.0 1.5 5.5 7.5 1.5 8.0 ns
5.0 1.5 6.5 8.5 1.5 9.0 ns
5.0 1.5 8.0 10.0 1.5 10.5 ns
5.0 1.0 5.5 7.5 1.0 8.0 ns
5.0 0.5 1.0 1.0 ns
Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by
design. Not tested.
AC Operating Requirements for ACTQ
Symbol
Parameter
tS Setup Time, HIGH or LOW
An or Bn to LEBA or LEAB
tS Hold Time, HIGH or LOW
An or Bn to LEBA or LEAB
tW Latch Enable
Pulse Width, LOW
Note 18: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 18)
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Typ
TA = −40°C to +85°C
CL = 50 pF
Guaranteed Minimum
3.0 3.0
1.5 1.5
4.0 4.0
Units
ns
ns
ns
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
70.0
Units
pF
pF
Conditions
VCC = OPEN
VCC = 5.0V
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