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74ACTQ16543SSC Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74ACTQ16543SSC
Beschreibung 16-Bit Registered Transceiver with 3-STATE Outputs
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 9 Seiten
74ACTQ16543SSC Datasheet, Funktion
December 1991
Revised December 1998
74ACTQ16543
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ACTQ16543 contains sixteen non-inverting transceiv-
ers containing two sets of D-type registers for temporary
storage of data flowing in either direction. Each byte has
separate control inputs which can be shorted together for
full 16-bit operation. Separate Latch Enable and Output
Enable inputs are provided for each register to permit inde-
pendent input and output control in either direction of data
flow.
The ACTQ16543 utilizes Fairchild Quiet Seriestechnol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Seriesfea-
tures GTOoutput control and undershoot corrector for
superior performance.
Features
s Utilizes Fairchild FACT Quiet Series technology
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Independent registers for A and B buses
s Separate controls for data flow in each direction
s Back-to-back registers for storage
Multiplexed real-time and stored data transfers
s Separate control logic for each byte
s 16-bit version of the ACTQ543
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output loading specs for both 50 pF and 250pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ16543SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16543MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Descriptions
OEABn
OEBAn
CEABn
CEBAn
LEABn
LEBAn
A0–A15
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B0–B15
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
FACT, Quiet Series, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010967.prf
www.fairchildsemi.com






74ACTQ16543SSC Datasheet, Funktion
Extended AC Electrical Characteristics
TA = −40 to +85°C
VCC = Com
TA = −40 to +85°C
Symbol
Parameter
CL = 50 pF
VCC = Com
Units
16 Outputs Switching
(Note 10)
CL = 250 pF
(Note 11)
Min Typ Max Min Max
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
Propagation Delay
Transparent Mode
An to Bn or Bn to An
Propagation Delay
LEBAn, LEABn to An, Bn
Output Enable Time
OEBAn or OEABn to An or Bn
4.5
3.7
4.3
3.7
4.0
4.3
11.1 5.8 14.3
9.6 5.1 13.4
11.3 6.2 16.3
9.7 5.8 14.9
10.7
11.3 (Note 12)
ns
ns
ns
tPHZ
tPLZ
CEBAn or CEABn to An or Bn
Output Disable Time
OEBAn or OEABn to An or Bn
3.0
2.8
8.0
7.6 (Note 13)
ns
tOSHL
(Note 14)
CEBAn or CEABn to An or Bn
Pin to Pin Skew
HL Data to Output
1.1 ns
tOSLH
(Note 14)
Pin to Pin Skew
LH Data to Output
1.4 ns
tOSHL
(Note 14)
Pin to Pin Skew
Latch to Output
2.6 ns
tOSLH
(Note 14)
Pin to Pin Skew
Latch to Output
1.0 ns
tOST
(Note 14)
Pin to Pin Skew
Data to Output
1.0
ns
tOST
(Note 14)
Pin to Pin Skew
Latch to Output
2.2 ns
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all low-to-high,
high-to-low, etc.).
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 12: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 13: The Output Disable Time is dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW to HIGH and/or HIGH to
LOW (tOST).
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation.Capacitance
Typ
4.5
95.0
Units
pF
pF
VCC = 5.0V
VCC = 5.0V
Conditions
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