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PDF 74ACTQ16373MEA Data sheet ( Hoja de datos )
| Número de pieza | 74ACTQ16373MEA | |
| Descripción | 16-Bit Transparent Latch with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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June 1991
Revised November 1999
74ACTQ16373
16-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACTQ16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is low, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state. The ACTQ16373 utilizes Fairchild’s Quiet
Series technology to guarantee quiet output switching
and improved dynamic threshold performance. FACT Quiet
Series features GTO output control for superior perfor-
mance.
Features
s Utilizes Fairchild FACT Quiet Series technology
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Separate control logic for each byte
s 16-bit version of the ACTQ373
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output Loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ16373MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OEn
LEn
I0–I15
O0–O15
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010934
www.fairchildsemi.com
1 page  
AC Operating Requirements
Symbol
Parameter
tS Setup Time, HIGH or LOW,
Input to Clock
tH Hold Time, HIGH or LOW
Input to Clock
tW CS Pulse Width,
HIGH or LOW
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
VCC
(V)
(Note 15)
5.0
5.0
5.0
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Guaranteed Minimum
3.0 3.0
1.5 1.5
4.0 4.0
Units
ns
ns
ns
Typ Units
Conditions
4.5 pF VCC = 5.0V
30 pF VCC = 5.0V
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74ACTQ16373MEA.PDF ] | |
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