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74ACTQ16373 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74ACTQ16373
Beschreibung 16-Bit Transparent Latch with 3-STATE Outputs
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 8 Seiten
74ACTQ16373 Datasheet, Funktion
June 1991
Revised November 1999
74ACTQ16373
16-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACTQ16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is low, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state. The ACTQ16373 utilizes Fairchild’s Quiet
Seriestechnology to guarantee quiet output switching
and improved dynamic threshold performance. FACT Quiet
Seriesfeatures GTOoutput control for superior perfor-
mance.
Features
s Utilizes Fairchild FACT Quiet Series technology
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Separate control logic for each byte
s 16-bit version of the ACTQ373
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output Loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ16373MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300Wide
74ACTQ16373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OEn
LEn
I0I15
O0O15
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Series, and GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010934
www.fairchildsemi.com






74ACTQ16373 Datasheet, Funktion
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
VOLP/VOLV and VOHP/V OHV:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Measure VOLP and VOLVon the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
VILD and VIHD:
Monitor one of the switching outputs using a 50coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD.
Next decrease the input HIGH voltage level, VIH until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as V IHD.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
Note A: VOHV and VOLP are measured with respect to ground reference.
Note B: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns,
tf = 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
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