Datenblatt-pdf.com


DT72V3654L10PF Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer DT72V3654L10PF
Beschreibung 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2/048 x 36 x 2 4/096 x 36 x 2 8/192 x 36 x 2
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 30 Seiten
DT72V3654L10PF Datasheet, Funktion
3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
IDT72V3654
IDT72V3664
IDT72V3674
FEATURES
Memory storage capacity:
IDT72V3654 – 2,048 x 36 x 2
IDT72V3664 – 4,096 x 36 x 2
IDT72V3674 – 8,192 x 36 x 2
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent clocked FIFOs buffering data in opposite
directions
Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
Programmable Almost-Empty and Almost-Full flags; each has five
default offsets (8, 16, 64, 256 and 1,024 )
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Retransmit Capability
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Auto power down minimizes power dissipation
Available in space saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible version of the 5V operating
IDT723654/723664/723674
Pin compatible to the lower density parts, IDT72V3624/72V3634/
72V3644
Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
FFA/IRA
AFA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
Mail 1
Register
36
RAM ARRAY
2,048 x 36
36
4,096 x 36
8,192 x 36
FIFO1
Write
Pointer
Read
Pointer
Status Flag
Logic
MBF1
36
EFB/ORB
AEB
FS2
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
Programmable Flag
Offset Registers
Timing
Mode
13
FIFO2
Status Flag
Logic
FWFT
B0-B35
FFB/IRB
AFB
RT1
RTM
RT2
36
FIFO1 and
FIFO2
Retransmit
Logic
MBF2
Read
Pointer
Write
Pointer
RAM ARRAY
36 2,048 x 36
4,096 x 36
8,192 x 36
Mail 2
Register
36
36
FIFO2,
Mail2
Reset
Logic
MRS2
PRS2
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4664 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-4664/4






DT72V3654L10PF Datasheet, Funktion
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
W/RA
W/RB
Name
Port-A Write/
Read Select
Port-B Write/
Read Select
I/O Description
I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
6

6 Page









DT72V3654L10PF pdf, datenblatt
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/
FWFT inputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and
CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB)
to indicate whether or not the FIFO memory has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed
by performing a formal read operation.
FollowingMasterReset,thelevelappliedtotheBE/FWFT inputtochoose
the desired timing mode must remain staticthroughoutFIFOoperation.Refer
to Figure 3 (Master Reset) for a First Word Fall Through select timing diagram.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
Four registers in the IDT72V3654/72V3664/72V3674 are used to hold the
offset values for the Almost-Empty and Almost-Full flags. The Port B Almost-
Empty flag (AEB) Offset register is labeled X1 and the Port A Almost-Empty
flag (AEA) Offset register is labeled X2. The Port A Almost-Full flag (AFA)
Offset register is labeled Y1 and the Port B Almost-Full flag (AFB) Offset register
is labeled Y2. The index of each register name corresponds to its FIFO number.
The offset registers can be loaded with preset values during the reset of a FIFO,
programmed in parallel using the FIFO’s Port A data inputs, or programmed
in serial using the Serial Data (SD) input (see Table 1).
FS0/SD, FS1/SEN and FS2 function the same way in both IDT Standard
and FWFT modes.
— PRESET VALUES
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers with
one of the five preset values listed in Table 1, the flag select inputs must be HIGH
or LOW during a master reset. For example, to load the preset value of 64 into
X1 and Y1, FS0, FS1 and FS2 must be HIGH when FlFO1 reset (MRS1) returns
HIGH. Flag-offset registers associated with FIFO2 are loaded with one of the
preset values in the same way with FIFO2 Master Reset (MRS2), toggled
simultaneously with FIFO1 Master Reset (MRS1). For relevant preset value
loading timing diagram, see Figure 3.
PARALLEL LOAD FROM PORT A
To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
Reset on both FlFOs simultaneously with FS2 HIGH or LOW, FS0 and FS1
LOW during the LOW-to-HIGH transition of MRS1 and MRS2. The state of FS2
at this point of reset will determine whether the parallel programming method
has Interspersed Parity or Non-Interspersed Parity. Refer to Table 1 for Flag
Programming Flag Offset setup . It is important to note that once parallel
programming has been selected during a Master Reset by holding both FS0
& FS1 LOW, these inputs must remain LOW during all subsequent FIFO
operation. They can only be toggled HIGH when future Master Resets are
performed and other programming methods are desired.
After this reset is complete, the first four writes to FIFO1 do not store data
in RAM but load the Offset registers in the order Y1, X1, Y2, X2. For Non-
Interspersed Parity mode the Port A data inputs used by the Offset registers are
(A10-A0), (A11-A0), or (A12-A0) for the IDT72V3654, IDT72V3664, or
IDT72V3674, respectively. For Interspersed Parity mode the Port A data inputs
used by the Offset registers are (A11-A9, A7-A0), (A12-A9, A7-A0), or (A13-
A9, A7-A0) for the IDT72V3654, IDT72V3664, or IDT72V3674, respectively.
The highest numbered input is used as the most significant bit of the binary
number in each case. Valid programming values for the registers range from
1 to 2,044 for the IDT72V3654; 1 to 4,092 for the IDT72V3664; and 1 to 8,188
for the IDT72V3674. After all the offset registers are programmed from Port A,
TABLE 1 — FLAG PROGRAMMING
FS2 FS1/SEN FS0/SD MRS1 MRS2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
H H H X
64
X
H H H X
X
64
H H L X
16
X
H H L X
X
16
H L H X
8
X
H L H X
X
8
L H H X
256
X
L H H X
X
256
L L H X
1,024
X
L L H X
X
1,024
L H L ↑↑
Serial programming via SD
H
LL
↑↑
Parallel programming via Port A(3,5)
L L L ↑↑
IP Mode(4, 5)
Serial programming via SD
Parallel programming via Port A(3,5)
IP Mode(4, 5)
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
3. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
4. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
5. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
12

12 Page





SeitenGesamt 30 Seiten
PDF Download[ DT72V3654L10PF Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
DT72V3654L10PF3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 2/048 x 36 x 2 4/096 x 36 x 2 8/192 x 36 x 2Integrated Device Technology
Integrated Device Technology

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche