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PDF DSP56852 Data sheet ( Hoja de datos )
| Número de pieza | DSP56852 | |
| Descripción | DSP56852 16-bit Digital Signal Processor | |
| Fabricantes | Motorola Inc | |
| Logotipo |  |
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Freescale Semiconductor, Inc.
DSP56852/D
Rev. 6.0 2/2004
DSP56852
Preliminary Technical Data
DSP56852 16-bit Digital Signal Processor
• 120 MIPS at 120MHz
• 6K x 16-bit Program SRAM
• 4K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• 21 External Memory Address lines, 16 data lines
and four chip selects
• One (1) Serial Port Interface (SPI) or one (1)
Improved Synchronous Serial Interface (ISSI)
• Interrupt Controller
• General Purpose 16-bit Quad Timer
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Computer Operating Properly (COP)/Watchdog
Timer
• 81-pin MAPBGA package
• Up to 11 GPIO
• One (1) Serial Communication Interface (SCI)
Memory
Program Memory
6144 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
4096 x 16 SRAM
6
JTAG/
Enhanced
OnCE
VDDIO
6
VDD VSSIO VSS VDDA VSSA
3 63
16-Bit
DSP56800E Core
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
System
Bus
Control
A0-16
A17-18 muxed (timer pins)
A19 muxed (CS3)
D0-D12[12:0]
D13-15 muxed (Mode A,B,C)
WR Enable
RD Enable
CS[2:0] muxed (GPIOA)
System
Address
Decoder
System
Device
IPBus Bridge (IPBB)
Peripheral
Address
Decoder
Decoding
Peripherals
Peripheral
Device
Selects
RW IPAB
Control
IPWDB
IPRDB
External Address
Bus Switch
External Data
Bus Switch
External Bus
Interface Unit
Bus Control
Clock
resets
SCI or
GPIOE
2
1 Quad
Timer
or A17,
A18
2
SSI or
SPI or
GPIOC
6
COP/
Watch-
dog
Interrupt
Controller
P
O
R
System
Integration
Module
PLL
Clock
Generator
O
S
C
IRQA
IRQB
3 CLKO
RESET
MODE
muxed (A20)
muxed (D13-15)
Figure 1. DSP56852 Block Diagram
XTAL
EXTAL
© Motorola, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the DSP56852 are organized into functional groups, as shown in Table 2
and as illustrated in Figure 2. In Table 3 each table row describes the package pin and the signal or signals
present.
Table 2. Functional Group Pin Allocations
Functional Group
Power (VDD, VDDIO, or VDDA)
Ground (VSS, VSSIO,or VSSA)
Phase Lock Loop (PLL) and Clock
External Bus Signals
External Chip Select*
Interrupt and Program Control
Synchronous Serial Interface (SSI) Port*
Serial Communications Interface (SCI) Port*
Serial Peripheral Interface (SPI) Port
Quad Timer Module Port
JTAG/Enhanced On-Chip Emulation (EOnCE)
*Alternately, GPIO pins
Number of Pins
101
101
22
393
34
35
6
2
06
07
6
1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA
2. CLKOUT is muxed Address pin A20.
3. Four Address pins are multiplexed with the timer, CS3 and CLKOUT pins.
4. CS3 is multiplexed with external Address Bus pin A19.
5. Mode pins are multiplexed with External Data pins D13-D15 like A17and A18.
6. Four of these pins are multiplexed with SSI.
7. Two of these pins are multiplexed with 2 bits of the External Address Bus A17and A18.
DSP56852 Technical Data
Preliminary
For More Information On This Product,
Go to: www.freescale.com
5
5 Page 
Freescale Semiconductor, Inc.
Introduction
Table 3. DSP56852 Signal and Package Information for the 81-pin MAPBGA
Pin No.
C4
Signal Name
MISO
Type
Input/Output
Description
SPI Master In/Slave Out (MISO)—This serial data pin is an
input to a master device and an output from a slave device.
The MISO line of a slave device is placed in the high-
impedance state if the slave device is not selected.
GPIOC4
Input/Output
Port C GPIO (4)—This pin is a General Purpose I/O (GPIO)
pin that can individually be programmed as input or output
pin.
SRCK
Input/Output
SSI Serial Receive Clock (SRCK)—This bidirectional pin
provides the serial bit rate clock for the receive section of the
SSI. The clock signal can be continuous or gated.
C5 MOSI
Input/
SPI Master Out/Slave In (MOSI)—This serial data pin is an
Output (Z) output from a master device and an input to a slave device.
The master device places data on the MOSI line a half-cycle
before the clock edge that the slave device uses to latch the
data.
GPIOC5
Input/Output
Port C GPIO (5)—This pin is a General Purpose I/O (GPIO)
pin that can individually be programmed as input or output
pin.
SRFS
Input/Output
SSI Serial Receive Frame Sync (SRFS)— This
bidirectional pin is used to count the number of words in a
frame while receiving. A programmable frame rate divider
and a word length divider are used for frame rate sync signal
generation.
A1 IRQA
Input
External Interrupt Request A (IRQA)—The IRQA Schmitt
trigger input is a synchronized external interrupt request that
indicates that an external device is requesting service. It can
be programmed to be level-sensitive or negative-edge-
triggered.
C2 IRQB
Input
External Interrupt Request B (IRQB)—The IRQB Schmitt
trigger input is an external interrupt request that indicates
that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-
triggered.
A6 EXTAL
Input
External Crystal Oscillator Input (EXTAL)—This input
should be connected to an external crystal. If an external
clock source other than a crystal oscillator is used, EXTAL
must be tied off.
A7
XTAL
Input/Output Crystal Oscillator Output (XTAL)—This output connects
the internal crystal oscillator output to an external crystal. If
an external clock source other than a crystal oscillator is
used, XTAL must be used as the input.
DSP56852 Technical Data
Preliminary
For More Information On This Product,
Go to: www.freescale.com
11
11 Page | ||
| Páginas | Total 44 Páginas | |
| PDF Descargar | [ Datasheet DSP56852.PDF ] | |
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