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PDF DSP56300FM Data sheet ( Hoja de datos )
| Número de pieza | DSP56300FM | |
| Descripción | high density CMOS device with 3.3 V inputs and outputs | |
| Fabricantes | Motorola Inc | |
| Logotipo |  |
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Technical Data
DSP56362/D
Rev. 3, 02/2004
24-Bit Audio Digital
Signal Processor
Freescale Semiconductor, Inc.
Motorola designed the DSP56362 to support digital audio applications requiring digital audio compression
and decompression, sound field processing, acoustic equalization, and other digital audio algorithms. The
DSP56362 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable
CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the
Motorola Symphony™ DSP family, as shown in Figure 1. This design provides a two-fold performance
increase over Motorola’s popular Symphony family of DSPs while retaining code compatibility. Significant
architectural enhancements include a barrel shifter, 24-bit addressing, instruction cache, and direct
memory access (DMA). The DSP56362 offers 100 million instructions per second (MIPS) using an internal
100 MHz clock at 3.3 V.
2 16
12 5
Triple
Timer
DAX
(SPDIF)
Address
Generation
Unit
Six Channel
DMA Unit
Internal
Data
Bus
Switch
Host
Interface ESAI SHI
Peripheral
Expansion Area
Program RAM/
Instruction
Cache
3072 × 24
Program ROM
30K × 24
Bootstrap ROM
192 × 24
X Data
RAM
5632 × 24
ROM
6144 × 24
Y Data
RAM
5632 × 24
ROM
6144 × 24
Memory
Expansion
Area
YAB
XAB
PAB
DAB
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
External
Address
Bus
Switch
18
Address
DRAM/SRAM
Bus
Interface
&
I - Cache
Control
11
Control
External
Data Bus
Switch
24
Data
EXTAL
CLKOUT
Clock
Generator
PLL
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24 × 24 + 56 → 56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Mngmnt.
JTAG
OnCE
6
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Figure 1 DSP56362 Block Diagram
AA0456G
This document contains information on a new product. Specifications and information herein are subject to change without notice.
IMOTOROLA
DSP56362 Advance Information
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
OVERVIEW
FEATURES
• Multimode, multichannel decoder software functionality
– Dolby Digital and Pro Logic
– MPEG2 5.1
– DTS
– Bass management
• Digital audio post-processing capabilities
– 3D Virtual surround sound
– Lucasfilm THX5.1
– Soundfield processing
– Equalization
• Digital Signal Processing Core
– 100 MIPS with a 100 MHz clock at 3.3 V +/- 5%
– Object code compatible with the DSP56000 core
– Highly parallel instruction set
– Data arithmetic logic unit (ALU)
• Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)
• 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)
• Conditional ALU instructions
• 24-bit or 16-bit arithmetic support under software control
– Program control unit (PCU)
• Position independent code (PIC) support
• Addressing modes optimized for DSP applications (including immediate offsets)
• On-chip instruction cache controller
• On-chip memory-expandable hardware stack
• Nested hardware DO loops
• Fast auto-return interrupts
– Direct memory access (DMA)
• Six DMA channels supporting internal and external accesses
• One-, two-, and three- dimensional transfers (including circular buffering)
MOTOROLA
DSP56362 Advance Information
For More Information On This Product,
Go to: www.freescale.com
1
5 Page 
POWER
Power
Name
VCCP
VCCQL (4)
VCCQH (3)
VCCA (3)
VCCD (4)
VCCC (2)
VCCH
VCCS (2)
Freescale Semiconductor, Inc.
Signal/Connection Descriptions
Power
Table 1-2 Power Inputs
Description
PLL Power—VCCP is VCC dedicated for PLL use. The voltage should be well-
regulated and the input should be provided with an extremely low impedance path
to the VCC power rail. There is one VCCP input.
Quiet Core (Low) Power—VCCQL is an isolated power for the core processing
logic. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors. There are four VCCQ inputs.
Quiet External (High) Power—VCCQH is a quiet power source for I/O lines. This
input must be tied externally to all other chip power inputs. The user must provide
adequate decoupling capacitors. There are three VCCQH inputs.
Address Bus Power—VCCA is an isolated power for sections of the address bus I/
O drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors. There are three VCCA
inputs.
Data Bus Power—VCCD is an isolated power for sections of the data bus I/O
drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors. There are four VCCD inputs.
Bus Control Power—VCCC is an isolated power for the bus control I/O drivers.
This input must be tied externally to all other chip power inputs. The user must
provide adequate external decoupling capacitors. There are two VCCC inputs.
Host Power—VCCH is an isolated power for the HDI08 I/O drivers. This input must
be tied externally to all other chip power inputs. The user must provide adequate
external decoupling capacitors. There is one VCCH input.
SHI, ESAI, DAX, and Timer Power—VCCS is an isolated power for the SHI, ESAI,
DAX, and Timer I/O drivers. This input must be tied externally to all other chip
power inputs. The user must provide adequate external decoupling capacitors.
There are two VCCS inputs.
MOTOROLA
DSP56362 Advance Information
For More Information On This Product,
Go to: www.freescale.com
1-3
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| PDF Descargar | [ Datasheet DSP56300FM.PDF ] | |
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