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DSM2190F4V-15T6 Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer DSM2190F4V-15T6
Beschreibung DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply)
Hersteller STMicroelectronics
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Gesamt 30 Seiten
DSM2190F4V-15T6 Datasheet, Funktion
DSM2190F4V
DSM (Digital Signal Processor System Memory)
For Analog Devices ADSP-2191 DSPs (3.3V Supply)
FEATURES SUMMARY
s Glueless Connection to DSP
– Easily add memory, logic, and I/O to the Exter-
nal Port of ADSP-2191 DSP
s Dual Flash Memories
– Two independent Flash memory arrays for stor-
ing DSP code and data. DSP may access the
two arrays concurrently (read from one while
erasing or writing the other)
– 256K x 8 Main Flash memory divided into 8 sec-
tors (32KByte each)
– Ample storage for booting DSP code/data
upon reset and subsequent code swaps
– Large capacity for data recording
– 32K x 8 Secondary Flash memory divided into 4
sectors (8 KByte each). Multiple uses:
– Small sector size ideal for small data sets,
and calibration or configuration constants
– Store custom start-up code in one or more
sectors and configure DSP to run from exter-
nal memory upon reset (no boot)
– Concatenate Secondary Flash with Main
Flash for total of 288 KBytes
– Each Flash sector can be write protected.
– Built-in programmable address decoding logic
allows mapping individual Flash sectors to any
address boundary
s Up to 16 Multifunction I/O Pins
– Increase total DSP system I/O capability
– I/O controlled by DSP software or PLD logic
s General purpose PLD
– Over 3,000 Gates of PLD with 16 macro cells
– Use for peripheral glue logic to keypads, control
panel, displays, LCDs, and other devices
– Eliminate PLDs and external logic devices
– Create state machines, chip selects, simple
shifters and counters, clock dividers, delays
– Simple PSDsoft ExpressTM software...Free
s Operating Range
– VCC: 3.3V±10%; Temperature: –40oC to +85oC
Figure 1. Packages
PQFP52 (T)
PLCC52 (K)
s In-System Programming (ISP) with JTAG
– Program entire chip in 10-25 seconds with no in-
volvement of the DSP
– Links with ADSP-2191 JTAG debug port
– Eliminate sockets for pre-programmed memory
and logic devices
– ISP allows efficient manufacturing and product
testing supporting Just-In-Time inventory
– Use low-cost FlashLINKTM cable with PC
s Content Security
– Programmable Security Bit blocks access of de-
vice programmers and readers
s Zero-Power Technology
– As low as 25µA standby current
s Packaging
– 52-pin PQFP or 52-pin PLCC
s Flash Memory Speed, Endurance, Retention
– 150 ns, 100K cycles, 15 year retention
September 2002
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DSM2190F4V-15T6 Datasheet, Funktion
DSM2190F4
ARCHITECTURAL OVERVIEW
Major functional blocks are shown in Figure 5.
DSP Address/Data/Control Interface
These DSP signals attach directly to the DSM for
a glueless connection. An 8-bit data connection is
formed and all 22 DSP address lines can be de-
coded as well as DSP memory strobes; BMS,
IOMS, and MSx. There are many different ways the
DSM2190F4 can be configured and used depend-
ing on system requirements. One convenient way
is to combine the function of the MSx signals into
the BMS signal. Doing this allows the DSP core to
access DSM memory at runtime even after the
boot process is complete using only the BMS sig-
nal. Combining MSx and BMS consumes less I/O
pin(s) on the DMS device. See Analog Devices
ADSP-2191 DSP Hardware Reference Manual,
Chapter 7, Code Example: BMS Runtime Access.
Alternatively, any of the MSx signals may also be
used to decode any of the sectors of DSM Main
Flash or Secondary flash memories.
Main Flash Memory
The 2M bit (256K x 8) Flash memory is divided into
eight equally-sized 32K byte sectors that are indi-
vidually selectable through the Decode PLD. Each
Flash memory sector can be located at any ad-
dress as defined by the user with PSDsoft Ex-
press. DSP code and data is easily placed in flash
memory using the PSDsoft Express software de-
velopment tool.
Secondary Flash Memory
The 256K bit (32K x 8) Flash memory is divided
into eight equally-sized 8K byte sectors that are in-
dividually selectable through the Decode PLD.
Each Flash memory sector can be located at any
address as defined by the user with PSDsoft Ex-
press. DSP code and data can also be placed
Secondary Flash memory using the PSDsoft Ex-
press development tool.
Secondary flash memory is good for storing data
because of its small sectors. Additionally, software
EEPROM emulation techniques can be used for
small data sets that change frequently on a byte-
by-byte basis.
Secondary flash may also be used to store custom
start-up code for applications that do not “boot” us-
ing DMA, but instead start executing code from ex-
ternal memory upon reset. Storing code here can
keep the entire Main Flash free of initialization
code for clean software partitioning. If only one or
more 8K byte sectors are needed for start-up
code, the remaining sectors of Secondary Flash
may be used for data storage.
Secondary Flash may also be used as an exten-
sion to Main Flash memory producing a total of
288K bytes
Miscellaneous: Main and Secondary Flash memo-
ries are totally independent, allowing concurrent
operation if needed. The DSP can read from one
memory while erasing or programming the other.
The DSP can erase Flash memories by individual
sectors or the entire Flash memory array may be
erased at one time. Each sector in either Flash
memory may be individually write protected, block-
ing any writes from the DSP (good for boot and
start-up code protection). The Flash memories au-
tomatically go to standby between DSP read or
write accesses to conserve power. Maximum ac-
cess times include sector decoding time. Maxi-
mum erase cycles is 100K and data retention is 15
years minimum. Flash memory, as well as the en-
tire DSM device may be programmed with the
JTAG ISP interface with no DSP involvement.
Programmable Logic (PLDs)
The DSM family contains two PLDS that may op-
tionally run in Turbo or Non-Turbo mode. PLDs op-
erate faster (less propagation delay) while in
Turbo mode but consume more power than Non-
Turbo mode. Non-Turbo mode allows the PLDs to
automatically go to standby when no inputs are
change to conserve power. The Turbo mode set-
ting is controlled at runtime by DSP software.
Decode PLD (DPLD). This is programmable log-
ic used to select one of the eight individual Main
Flash memory segments, one of four individual
Secondary Flash memory segments, or the group
of control registers within the DSM device. The
DPLD can also optionally drive external chip select
signals on Port D pins. DPLD input signals include:
DSP address and control signals, Page Register
outputs, DSM Port Pins, CPLD logic feedback.
Complex PLD (CPLD). This programmable logic
is used to create both combinatorial and sequen-
tial general purpose logic. The CPLD contains 16
Output Macrocells (OMCs) and 16 Input Macro-
cells (IMCs). PSD Macrocell registers are unique
in that that have direct connection to the DSP data
bus allowing them to be loaded and read directly
by the DSP at runtime. This direct access is good
for making small peripheral devices (shifters,
counters, state machines, etc.) that are accessed
directly by the DSP with little overhead. DPLD in-
puts include DSP address and control signals,
Page Register outputs, DSM Port Pins, and CPLD
feedback.
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6 Page









DSM2190F4V-15T6 pdf, datenblatt
DSM2190F4
TYPICAL MEMORY MAP
There many different ways to place (or map) the
addresses of DSM memory and I/O depending on
system requirements. The DPLD allows complete
mapping flexibility. Figure 7 shows one possible
system memory map. In this case, the DSP will
bootload (via DMA) the contents of Main Flash
memory upon reset. The Secondary Flash memo-
ry can be used for parameter storage or additional
code storage. BMS and MSx are configured in the
DSP to be combined into the BMS signal, allowing
the DSP to access both Flash memories at runt-
ime (after DMA boot). The DSP may execute code
directly from the DSM and well as erase and write
new code or data to DSM Flash.
The nomenclature fs0..fs7 are designators for the
individual sectors of Main Flash memory, 32K
bytes each. csboot0..csboot3 are designators for
the individual Secondary Flash memory seg-
ments, 8K bytes each. csiop designates the DSM
control register block.
The designer may easily specify memory mapping
in a point-and-click software environment using
PSDsoft ExpressTM.
12/61

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