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5384VA Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer 5384VA
Beschreibung In-System Programmable 3.3V SuperWIDE High Density PLD
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 28 Seiten
5384VA Datasheet, Funktion
ispLSI® 5384VA
In-System Programmable
3.3V SuperWIDE™ High Density PLD
Features
• SuperWIDE HIGH-DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 18,000 PLD Gates / 384 Macrocells
— Up to 288 I/O Pins
— 384 Registers
— High-Speed Global Interconnect
— SuperWIDE 32 Generic Logic Block (GLB) Size for
Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast
Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package
Options
— Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 125 MHz Maximum Operating Frequency
tpd = 7.5 ns Propagation Delay
— Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns,
tsu3 (CLK2/3) = 3.5ns
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with Single-
Level Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports
up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Macrocell Registers Feature Multiple Control
Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell
Product Term Clocks
— Slew and Skew Programmable I/O (SASPI/O™)
Supports Programmable Bus Hold, Pull-up, Open
Drain and Slew and Skew Rate Options
— Six Global Output Enable Terms, Two Global OE
Pins and One Product Term OE per Macrocell
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Boundary
Scan
Interface
Global Routing Pool
(GRP)
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
ispLSI 5000V Description
The ispLSI 5000V Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
Outputs from the GLBs drive the Global Routing Pool
(GRP) between the GLBs. Switching resources are pro-
vided to allow signals in the Global Routing Pool to drive
any or all the GLBs in the device. This mechanism allows
fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated,
programmable AND-array with 160 logic product terms
and five extra control product terms. The GLB has 68
inputs from the Global Routing Pool which are available
in both true and complement form for every product term.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
5384va_04
1






5384VA Datasheet, Funktion
Specifications ispLSI 5384VA
Figure 4. ispLSI 5000V Macrocell
PTOE
GOE0
GOE1
TOE
Global PTOE 0
Global PTOE 1
Global PTOE 2
Global PTOE 3
Global PTOE 4
Global PTOE 5
PTSA bypass
PTSA
Shared PT Clock 0
PT Clock Shared PT Clock 1
CLK0
CLK1
CLK2
CLK3
PT Reset
VCCIO VCC VCCIO
DQ
D/T
Clk En
R/L
Clk
RP
D
Delay
Slew Open
rate drain
2.5V/3.3V
Output
I/O Pad
To GRP
DQ
Q
Programmable
Speed/Power
Option
SET/RESET
PT Preset
Shared PT (P)reset 0
Shared PT (P)reset 1
D/T
Clk En
Clk
Register/
Latch
RP
6

6 Page









5384VA pdf, datenblatt
Specifications ispLSI 5384VA
DC Electrical Characteristics for 2.5V Range1
Over Recommended Operating Conditions
SYMBOL
PARAMETER
VCCIO I/O Reference Voltage
VIL Input Low Voltage
VIH Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
1. I/O voltage configuration must be set to VCCIO.
CONDITION
VOH(min) VOUT or VOUT VOL(max)
VOH(min) VOUT or VOUT VOL(max)
VCCIO=min, VIN=VIH or VIL, IOL= 100µA
VCCIO=min, VIN=VIH or VIL, IOL= 2mA
VCCIO=min, VIN=VIH or VIL, IOH= -100µA
VCCIO=min, VIN=VIH or VIL, IOH= -2mA
MIN.
2.3
-0.3
1.7
2.1
1.7
TYP.
MAX. UNITS
2.7 V
0.7 V
5.25 V
0.2 V
0.7 V
–V
–V
2.5V/5384VA
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
IIL Input or I/O Low Leakage Current
IIH Input or I/O High Leakage Current
IPU1
IBHL
IBHH
IBHLO
IBHLH
IBHT
IVCCIO
I/O Active Pullup Current
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current
Bus Hold Low Overdrive Current
Bus Hold High Overdrive Current
Bus Hold Trip Points
Current Needed for VCCIO Pin
CONDITION
0V VINVIL(Max.)
(VCCIO-0.2)V VIN VCCIO
VCCIO VIN 5.25V
0V VIN VIL
VIN = VIL(max)
VIN = VIH(min)
0V VIN VCCIO
0V VIN VCCIO
All I/Os Pulled-up, (Total I/Os * IPUmax)
1. Pullup is capable of pulling to a minimum voltage of VOH under no-load conditions.
MIN.
40
-40
VIL
TYP.
MAX. UNITS
-10 µA
10 µA
50 µA
-150 µA
µA
µA
550 µA
-550 µA
VIH V
45 mA
DC Char_5384VA
12

12 Page





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