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PDF DM74LS126A Data sheet ( Hoja de datos )
| Número de pieza | DM74LS126A | |
| Descripción | Quad 3-STATE Buffer | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1986
Revised March 2000
DM74LS126A
Quad 3-STATE Buffer
General Description
This device contains four independent gates each of which
performs a non-inverting buffer function. The outputs have
the 3-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned OFF presenting a high-imped-
ance state to the bus line. Thus the output will act neither
as a significant load nor as a driver. To minimize the possi-
bility that two outputs will attempt to take a common bus to
opposite logic levels, the disable time is shorter than the
enable time of the outputs.
Ordering Code:
Order Number Package Number
Package Description
DM74LS126AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS126AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y=A
Inputs
AC
LH
HH
XL
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
Hi-Z = 3-STATE (Outputs are disabled)
Output
Y
L
H
Hi-Z
© 2000 Fairchild Semiconductor Corporation DS006388
www.fairchildsemi.com
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| PDF Descargar | [ Datasheet DM74LS126A.PDF ] | |
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| DM74LS126A | Quad 3-STATE Buffer | Fairchild Semiconductor |
| DM74LS126AM | Quad 3-STATE Buffer | Fairchild Semiconductor |
| DM74LS126AN | Quad 3-STATE Buffer | Fairchild Semiconductor |
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