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FQP17P10 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer FQP17P10
Beschreibung 100V P-Channel MOSFET
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 8 Seiten
FQP17P10 Datasheet, Funktion
FQP17P10
100V P-Channel MOSFET
QFET TM
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as audio amplifier,
high efficiency switching DC/DC converters, and DC motor
control.
Features
• -16.5A, -100V, RDS(on) = 0.19@VGS = -10 V
• Low gate charge ( typical 30 nC)
• Low Crss ( typical 100 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• 175°C maximum junction temperature rating
D
GDS
TO-220
FQP Series
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
RθCS
RθJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case-to-Sink
Thermal Resistance, Junction-to-Ambient
G
S
FQP17P10
-100
-16.5
-11.7
-66
± 30
580
-16.5
10
-6.0
100
0.67
-55 to +175
300
Typ Max
-- 1.5
0.5 --
-- 62.5
©2002 Fairchild Semiconductor Corporation
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Units
°C/W
°C/W
°C/W
Rev. B, August 2002






FQP17P10 Datasheet, Funktion
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
I SD
Driver
RG
VGS
+
VDS
_
L
Compliment of DUT
(N-Channel)
• dv/dt controlled by RG
• ISD controlled by pulse period
VDD
VGS
( Driver )
I SD
( DUT )
VDS
( DUT )
D = --G--a--t-e--P--u--l-s-e---W---i-d-t-h--
Gate Pulse Period
10V
Body Diode Reverse Current
IRM
IFM , Body Diode Forward Current
VSD
di/dt
Body Diode
Forward Voltage Drop
Body Diode Recovery dv/dt
VDD
©2002 Fairchild Semiconductor Corporation
Rev. B, August 2002

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