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Teilenummer | FQP13N10L |
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Beschreibung | 100V LOGIC N-Channel MOSFET | |
Hersteller | Fairchild Semiconductor | |
Logo | ||
Gesamt 8 Seiten FQP13N10L
100V LOGIC N-Channel MOSFET
December 2000
QFETTM
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology is especially tailored to minimize
on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation modes. These devices are
well suited for low voltage applications such as high
efficiency switching DC/DC converters, and DC motor
control.
Features
• 12.8A, 100V, RDS(on) = 0.18Ω @VGS = 10 V
• Low gate charge ( typical 8.7 nC)
• Low Crss ( typical 20 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• 175°C maximum junction temperature rating
GD S
TO-220
FQP Series
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8” from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
RθCS
RθJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Case-to-Sink
Thermal Resistance, Junction-to-Ambient
D
!
"
!"
G!
"
"
!
S
FQP13N10L
100
12.8
9.05
51.2
± 20
95
12.8
6.5
6.0
65
0.43
-55 to +175
300
Typ Max
-- 2.31
0.5 --
-- 62.5
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Units
°C/W
°C/W
°C/W
©2000 Fairchild Semiconductor International
Rev. A4, December 2000
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
I SD
L
Driver
RG
VGS
Same Type
as DUT
• dv/dt controlled by RG
• ISD controlled by pulse period
VDD
VGS
( Driver )
I SD
( DUT )
VDS
( DUT )
D
=
--G--a--t-e--P--u--l-s-e---W---i-d-t-h--
Gate Pulse Period
10V
IFM , Body Diode Forward Current
di/dt
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VSD
Body Diode
Forward Voltage Drop
VDD
©2000 Fairchild Semiconductor International
Rev. A4, December 2000
6 Page | ||
Seiten | Gesamt 8 Seiten | |
PDF Download | [ FQP13N10L Schematic.PDF ] |
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