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Teilenummer | FQD3P20 |
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Beschreibung | 200V P-Channel MOSFET | |
Hersteller | Fairchild Semiconductor | |
Logo | ||
Gesamt 9 Seiten FQD3P20 / FQU3P20
200V P-Channel MOSFET
April 2000
QFETTM
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters.
Features
• -2.4A, -200V, RDS(on) = 2.7Ω @VGS = -10 V
• Low gate charge ( typical 6.0 nC)
• Low Crss ( typical 7.5 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
DS
!
GS
D-PAK
FQD Series
GDS
I-PAK
FQU Series
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
Parameter
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Drain-Source Voltage
Drain Current
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
- Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (TA = 25°C) *
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8from case for 5 seconds
G!
!
D
FQD3P20 / FQU3P20
-200
-2.4
-1.52
-9.6
±30
150
-2.4
3.7
-5.5
2.5
37
0.29
-55 to +150
300
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W
W/°C
°C
°C
Thermal Characteristics
Symbol
RθJC
RθJA
RθJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
* When mounted on the minimum pad size recommended (PCB Mount)
©2000 Fairchild Semiconductor International
Typ
Max
Units
-- 3.4 °CW
-- 50 °CW
-- 110 °CW
Rev. A, April 2000
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
I SD
Driver
RG
VGS
+
VDS
_
L
Compliment of DUT
(N-Channel)
• dv/dt controlled by RG
• ISD controlled by pulse period
VDD
VGS
( Driver )
I SD
( DUT )
VDS
( DUT )
D = --G--a--t-e--P--u--l-s-e---W---i-d-t-h--
Gate Pulse Period
10V
Body Diode Reverse Current
IRM
IFM , Body Diode Forward Current
VSD
di/dt
Body Diode
Forward Voltage Drop
Body Diode Recovery dv/dt
VDD
©2000 Fairchild Semiconductor International
Rev. A, April 2000
6 Page | ||
Seiten | Gesamt 9 Seiten | |
PDF Download | [ FQD3P20 Schematic.PDF ] |
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