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M27C1001-10F3TR Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer M27C1001-10F3TR
Beschreibung 1 Mbit 128Kb x8 UV EPROM and OTP EPROM
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 17 Seiten
M27C1001-10F3TR Datasheet, Funktion
M27C1001
1 Mbit (128Kb x8) UV EPROM and OTP EPROM
s 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
s ACCESS TIME: 35ns
s LOW POWER CONSUMPTION:
– Active Current 30mA at 5Mhz
– Standby Current 100µA
s PROGRAMMING VOLTAGE: 12.75V ± 0.25V
s PROGRAMMING TIME: 100µs/word
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 05h
DESCRIPTION
The M27C1001 is a 1 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large programs and
is organized as 131,072 words of 8 bits.
The FDIP32W (window ceramic frit-seal package)
and the LCCC32W (leadless chip carrier package)
have a transparent lids which allow the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C1001 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
32
1
FDIP32W (F)
32
1
PDIP32 (B)
LCCC32W (L)
PLCC32 (K)
Figure 1. Logic Diagram
TSOP32 (N)
8 x 20 mm
VCC VPP
17
A0-A16
8
Q0-Q7
P M27C1001
E
G
VSS
AI00710B
January 2000
1/17






M27C1001-10F3TR Datasheet, Funktion
M27C1001
Table 8B. Read Mode AC Characteristics (1)
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C1001
Symbol Alt
Parameter
Test Condition
-80
-90
-10
-12/-15/
-20/-25
Unit
Min Max Min Max Min Max Min Max
tAVQV
tACC
Address Valid to
Output Valid
E = VIL, G = VIL
80
90 100 120 ns
tELQV
tCE
Chip Enable Low to
Output Valid
G = VIL
80 90 100 120 ns
tGLQV
tOE
Output Enable Low
to Output Valid
E = VIL
40 45 50 60 ns
tEHQZ (2)
tDF
Chip Enable High to
Output Hi-Z
G = VIL
0 30 0 30 0 30 0 40 ns
tGHQZ (2)
tDF
Output Enable High
to Output Hi-Z
E = VIL
0 30 0 30 0 30 0 40 ns
tAXQX
tOH
Address Transition
to Output Transition
E = VIL, G = VIL
0
0
0
0
ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A16
E
G
Q0-Q7
VALID
tAVQV
tGLQV
tELQV
tAXQX
VALID
tEHQZ
tGHQZ
Hi-Z
AI00713B
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
6/17

6 Page









M27C1001-10F3TR pdf, datenblatt
M27C1001
Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 5.72 0.225
A1 0.51 1.40
0.020
0.055
A2 3.91 4.57
0.154
0.180
A3 3.89 4.50
0.153
0.177
B
0.41 0.56
0.016
0.022
B1 1.45
– 0.057 –
C
0.23 0.30
0.009
0.012
D
41.73
42.04
1.643
1.655
D2 38.10
– 1.500 –
E 15.24
– 0.600 –
E1
13.06
13.36
0.514
0.526
e 2.54
– 0.100 –
eA 14.99
– 0.590 –
eB
16.18
18.03
0.637
0.710
L 3.18
0.125
S
1.52 2.49
0.060
0.098
7.11
– 0.280 –
α 4° 11°
4° 11°
N 32
32
Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Outline
A2 A3 A
A1 L
B1 B e
D2
S
N
D
E1 E
1
Drawing is not to scale.
12/17
α
C
eA
eB
FDIPW-a

12 Page





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