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PDF M27256 Data sheet ( Hoja de datos )
| Número de pieza | M27256 | |
| Descripción | NMOS 256K 32K x 8 UV EPROM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de M27256 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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M27256
NMOS 256K (32K x 8) UV EPROM
FAST ACCESS TIME: 170ns
EXTENDED TEMPERATURE RANGE
SINGLE 5V SUPPLY VOLTAGE
LOW STANDBY CURRENT: 40mA max
TTL COMPATIBLE DURING READ and
PROGRAM
FAST PROGRAMMING ALGORITHM
ELECTRONIC SIGNATURE
PROGRAMMING VOLTAGE: 12V
28
1
FDIP28W (F)
DESCRIPTION
The M27256 is a 262,144 bit UV erasable and
electrically programmable memory EPROM. It is
organized as 32.768 words by 8 bits.
The M27256 is housed in a 28 pin Window Ceramic
Frit-Seal Dual-in-Line package. The transparent lid
allows the user to expose the chip to ultraviolet light
to erase the bit pattern. A new pattern can then be
written to the device by following the programming
procedure.
Figure 1. Logic Diagram
VCC VPP
15
A0-A14
8
Q0-Q7
Table 1. Signal Names
A0 - A14
Q0 - Q7
E
G
VPP
VCC
VSS
Address Inputs
Data Outputs
Chip Enable
Output Enable
Program Supply
Supply Voltage
Ground
E M27256
G
VSS
AI00767B
March 1995
1/10
1 page  
M27256
Table 6. Read Mode DC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol
Parameter
Test Condition
Min
ILI Input Leakage Current
0 ≤ VIN ≤ VCC
ILO Output Leakage Current
VOUT = VCC
ICC Supply Current
E = VIL, G = VIL
ICC1 Supply Current (Standby)
E = VIH
IPP Program Current
VPP = VCC
VIL Input Low Voltage
–0.1
VIH Input High Voltage
2
VOL Output Low Voltage
IOL = 2.1mA
VOH Output High Voltage
IOH = –400µA
2.4
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Max
±10
±10
100
40
5
0.8
VCC + 1
0.45
Unit
µA
µA
mA
mA
mA
V
V
V
V
Table 7A. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Alt
Parameter
tAVQV
tACC
Address Valid to
Output Valid
tELQV
tCE
Chip Enable Low
to Output Valid
tGLQV
tOE
Output Enable
Low to Output Valid
tEHQZ (2)
tDF
Chip Enable High
to Output Hi-Z
tGHQZ (2)
tDF
Output Enable
High to Output Hi-Z
tAXQX
tOH
Address Transition
to Output Transition
Test
Condition
E = VIL,
G = VIL
G = VIL
-1
Min Max
170
170
E = VIL
70
G = VIL 0 35
E = VIL 0 35
E = VIL,
G = VIL
0
M27256
-2, -20
Min Max
200
200
75
0 55
0 55
0
blank, -25
Min Max
250
250
100
0 60
0 60
0
Table 7B. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Alt
Parameter
Test
Condition
M27256
-3 -4
Min Max Min Max
tAVQV
tACC
Address Valid to
Output Valid
E = VIL,
G = VIL
300
450
tELQV
tCE
Chip Enable Low
to Output Valid
G = VIL
300
450
tGLQV
tOE
Output Enable
Low to Output Valid
E = VIL,
120
150
tEHQZ (2)
tDF
Chip Enable High
to Output Hi-Z
G = VIL
0
105
0
130
tGHQZ (2)
tDF
Output Enable
High to Output Hi-Z
E = VIL
0
105
0
130
tAXQX
tOH
Address Transition
to Output Transition
E = VIL,
G = VIL
0
0
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
5/10
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet M27256.PDF ] | |
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