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FDS6612A Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer FDS6612A
Beschreibung PowerTrench MOSFET
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 8 Seiten
FDS6612A Datasheet, Funktion
FDS6612A
Single N-Channel, Logic-Level, PowerTrench® MOSFET
April 2007
tm
General Description
This N-Channel Logic Level MOSFET is produced
using Fairchild Semiconductor’s
advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
Features
8.4 A, 30 V.
RDS(ON) = 22 m@ VGS = 10 V
RDS(ON) = 30 m@ VGS = 4.5 V
Fast switching speed
Low gate charge
High performance trench technology for extremely
low RDS(ON)
High power and current handling capability
DD DDDD
DD
SO-8
Pin 1 SO-8
SS SS SS GG
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol
Parameter
VDSS
VGSS
ID
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
– Pulsed
(Note 1a)
PD
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
EAS Single Pulse Avalanche Energy
(Note 3)
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
RθJA Thermal Resistance, Junction-to-Ambient
RθJC Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1b)
(Note 1)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
FDS6612A
FDS6612A
13’’
5
6
7
8
Ratings
30
±20
8.4
40
2.5
1.0
24
–55 to +150
50
125
25
Tape width
12mm
4
3
2
1
Units
V
V
A
W
mJ
°C
°C/W
Quantity
2500 units
©2007 Fairchild Semiconductor Corporation
FDS6612A Rev D1 (W)






FDS6612A Datasheet, Funktion
PSPICE Electrical Model N-Channel
.SUBCKT FDS6612A 2 1 3
*NOM TEMP=25 DEG C
*REV A - JULY 2003
CA 12 8 1E-9
CB 15 14 4.0E-10
CIN 6 8 5.1E-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 34.2
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LGATE 1 9 3.84E-9
LDRAIN 2 5 1.00E-9
LSOURCE 3 7 4E-9
GATE
1
RLGATE 1 9 38.4
RLDRAIN 2 5 10
RLSOURCE 3 7 40
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 8E-3
RGATE 9 20 4.2
RSLC1 5 51 RSLCMOD 1E-6
RSLC2 5 50 1E3
RSOURCE 8 7 RSOURCEMOD 7.5E-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
LGATE
RLGA TE
D PLC AP
10
RSLC2
5
RSLC1
51
5
51
ESLC
DBREA K
11
L DRA IN
RL DRA IN
DRA IN
2
-
ESG
6
8
+ EVTHRES
EVTEMP
+ 19 -
8
RGATE + 18 - 6
9 20 22
50
R DRA IN
21 16
EBREA K
+
17
18
-
MWEAK
MMED
MSTRO
D BODY
CIN 8
S1A
12 13
8
S2A
14
13
15
RSOUR CE
7
LSOURC E
SOURC E
3
RLSOU RCE
RBR EAK
17 18
S1 B
S2B
CA
13 CB
+ + 14
EGS
6
8
EDS
5
8
--
RVTEMP
19
IT -
VBA T
+
8
22
RVTHR ES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1E-6*105),3))}
.MODEL DBODYMOD D (IS=7E-15 RS=6.1E-3 N=0.84 TRS1=1.7E-3 TRS2=1.0E-6
+ CJO=3.2E-10 TT=10E-9 M=0.5 IKF=0.3 XTI=3.0)
.MODEL DBREAKMOD D (RS=1E-1 TRS1=1.12E-3 TRS2=1.25E-6)
.MODEL DPLCAPMOD D (CJO=14E-11 IS=1E-30 N=10 M=0.34)
.MODEL MWEAKMOD NMOS (VTO=1.82 KP=0.05 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=42 RS=.1)
.MODEL MMEDMOD NMOS (VTO=2.1 KP=6 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=4.2)
.MODEL MSTROMOD NMOS (VTO=2.55 KP=50 IS=1E-30 N=10 TOX=1 L=1U W=1U)
.MODEL RBREAKMOD RES (TC1=0.83E-3 TC2=1E-7)
.MODEL RDRAINMOD RES (TC1=6E-3 TC2=5E-6)
.MODEL RSLCMOD RES (TC1=2.5E-3 TC2=4.5E-6)
.MODEL RSOURCEMOD RES (TC1=1.0E-3 TC2=1E-6)
.MODEL RVTHRESMOD RES (TC1=-2.013E-3 TC2=-7E-6)
.MODEL RVTEMPMOD RES (TC1=-1.5E-3 TC2=1E-6)
.MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.3 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-0.5 VOFF=-1.3)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
FDS6612A Rev D1 (W)

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