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FDS4953 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer FDS4953
Beschreibung Dual P-Channel/ Logic Level/ PowerTrenchTM MOSFET
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 8 Seiten
FDS4953 Datasheet, Funktion
February 1999
FDS4953
Dual P-Channel, Logic Level, PowerTrenchTM MOSFET
General Description
These P-Channel Logic Level MOSFETs are
produced using Fairchild Semiconductor's advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain low
gate charge for superior switching performance.
These devices are well suited for portable electronics
applications: load switching and power management,
battery charging circuits, and DC/DC conversion.
Features
-5 A, -30 V. RDS(ON) = 0.053 @ VGS = -10 V,
RDS(ON) = 0.095 @ VGS = -4.5V.
Low gate charge (8nC typical).
High performance trench technology for extremely low
RDS(ON).
High power and current handling capability.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
D2
D2
D1
D1
FD49S53
SO-8
G2
S2
pin 1
G1
S1
SO-8
SOT-223
5
6
7
8
Absolute Maximum Ratings
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current - Continuous
- Pulsed
TA = 25oC unless otherwise noted
(Note 1a)
PD Power Dissipation for Dual Operation
Power Dissipation for Single Operation (Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
© 1999 Fairchild Semiconductor Corporation
Ratings
-30
±20
-5
-20
2
1.6
1
0.9
-55 to 150
78
40
SOIC-16
4
3
2
1
Units
V
V
A
W
°C
°C/W
°C/W
FDS4953 Rev.C






FDS4953 Datasheet, Funktion
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0
T
P0
D0
K0
Wc
B0
Tc
A0 P1 D1
User Direction of Feed
E1
F
E2
W
Dimensions are in millimeter
Pkg type
A0
SOIC(8lds) 6.50
(12mm)
+/-0.10
B0
5.30
+/-0.10
W
12.0
+/-0.3
D0 D1 E1 E2
1.55
+/-0.05
1.60
+/-0.10
1.75
+/-0.10
10.25
min
F P1
5.50
+/-0.05
8.0
+/-0.1
P0
4.0
+/-0.1
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum
Typical
component
cavity
B0 center line
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
SOIC(8lds) Reel Configuration: Figure 4.0
Typical
component
A0 center line
Sketch B (Top View)
Component Rotation
K0
2.1
+/-0.10
T
0.450
+/-
0.150
Wc
9.2
+/-0.3
Tc
0.06
+/-0.02
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
W1 Measured at Hub
Dim A
Max
Dim A
max
Dim N
See detail AA
7" Diameter Option
B Min
Dim C
See detail AA
Dim D
W3 min
13" Diameter Option
W2 max Measured at Hub
Tape Size
Reel
Option
12mm
7" Dia
12mm
13" Dia
Dimensions are in inches and millimeters
Dim A Dim B
Dim C
7.00
177.8
13.00
330
0.059
1.5
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
512 +0.020/-0.008
13 +0.5/-0.2
Dim D
0.795
20.2
0.795
20.2
Dim N
2.165
55
7.00
178
Dim W1
0.488 +0.078/-0.000
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
DETAIL AA
Dim W2
0.724
18.4
0.724
18.4
Dim W3 (LSL-USL)
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
© 1998 Fairchild Semiconductor Corporation
July 1999, Rev. B

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