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FDC37N869TQFP Schematic ( PDF Datasheet ) - ETC

Teilenummer FDC37N869TQFP
Beschreibung 5V and 3.3V Super I/O Controller with Infrared Support for Portable Applications
Hersteller ETC
Logo ETC Logo 




Gesamt 30 Seiten
FDC37N869TQFP Datasheet, Funktion
FDC37N869
5V and 3.3V Super I/O Controller with Infrared Support for
Portable Applications
FEATURES
§ PC 99 Compliant
§ 5 Volt and 3.3 Volt Operation
§ Intelligent Auto Power Management
§ 16 Bit Address Qualification
§ 2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller
- Software and Register Compatible with
SMSC’s Proprietary 82077AA Compatible
Core
- Supports One Floppy Drive Directly
- Configurable Open Drain/Push-Pull Output
Drivers
- Supports Vertical Recording Format
- 16 Byte Data FIFO
- 100% IBM Compatibility
- Detects All Overrun and Underrun Conditions
- Sophisticated Power Control Circuitry (PCC)
Including Multiple Power-Down Modes for
Reduced Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
- Swap Drives A and B
- Non-Burst Mode DMA Option
- 48 Base I/O Address, 15 IRQ and 4 DMA
Options
- Forceable Write Protect and Disk Change
Controls
§ Floppy Disk Available on Parallel Port Pins
ACPI Compliant
§ Enhanced Digital Data Separator
- 2Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation Modes
§ Serial Ports
- Two High Speed NS16C550 Compatible
UARTs with Send/Receive 16 Byte FIFOs
- Supports 230k and 460k Baud
- Programmable Baud Rate Generator
- Modem Control Circuitry
§ Infrared Communications Controller
- IrDA v1.1 (4Mbps), HPSIR, ASKIR, Consumer
IR Support
- 2 IR Ports
- 96 Base I/O Address, 15 IRQ Options and 4
DMA Options
§ Multi-Mode Parallel Port with ChiProtect
- Standard Mode
- IBM PC/XT, PC/AT, and PS/2 Compatible Bi-
directional Parallel Port
- Enhanced Parallel Port (EPP) Compatible
- EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)
- Enhanced Capabilities Port (ECP)
Compatible (IEEE 1284 Compliant)
- Incorporates ChiProtect Circuitry for Protection
Against Damage Due to Printer Power-On
- 192 Base I/O Address, 15 IRQ and 4 DMA
Options
§ Game Port Select Logic
- 48 Base I/O Addresses
§ General Purpose Address Decoder
- 16-Byte Block Decode
SMSC DS – FDC37N869
ORDERING INFORMATION
Order Number: FDC37N869TQFP
100 Pin TQFP Package
11/09/2000






FDC37N869TQFP Datasheet, Funktion
Description ............................................................................................................................... 82
Register Definitions................................................................................................................... 83
OPERATION.............................................................................................................................. 89
AUTO POWER MANAGEMENT ......................................................................................................... 93
FDC POWER MANAGEMENT ............................................................................................................... 93
DSR From Powerdown.............................................................................................................. 93
Wake Up From Auto Powerdown .............................................................................................. 93
Register Behavior...................................................................................................................... 94
Pin Behavior ............................................................................................................................. 94
UART POWER MANAGEMENT ............................................................................................................. 96
PARALLEL PORT.............................................................................................................................. 96
SERIAL IRQ .................................................................................................................................. 96
Introduction .............................................................................................................................. 96
IRQSER Cycle Modes................................................................................................................ 97
IRQSER IRQ/Data Frames .......................................................................................................... 98
Stop Cycle Control.................................................................................................................... 99
Latency..................................................................................................................................... 99
EOI/ISR Read Latency ............................................................................................................... 99
AC/DC Specification Issue......................................................................................................... 99
Reset and Initialization................................................................................................................ 99
ADD PCI NCLKRUN SUPPORT.................................................................................................... 100
Overview................................................................................................................................. 100
Using nCLKRUN...................................................................................................................... 100
CONFIGURATION........................................................................................................................... 101
CONFIGURATION ACCESS PORTS........................................................................................................ 101
CONFIGURATION STATE.................................................................................................................... 102
Entering the Configuration State............................................................................................. 102
Configuration Register Programming...................................................................................... 102
Exiting the Configuration State ............................................................................................... 102
Programming Example........................................................................................................... 102
Configuration Select Register (CSR)........................................................................................ 103
CONFIGURATION REGISTERS DESCRIPTION ............................................................................................ 103
CR00....................................................................................................................................... 104
CR01....................................................................................................................................... 104
CR02....................................................................................................................................... 106
CR03....................................................................................................................................... 106
CR04....................................................................................................................................... 107
CR05....................................................................................................................................... 108
CR06....................................................................................................................................... 108
CR07....................................................................................................................................... 109
CR08....................................................................................................................................... 109
CR09....................................................................................................................................... 109
CR0A ...................................................................................................................................... 110
CR0B ...................................................................................................................................... 110
CR0C ...................................................................................................................................... 111
CR0D ...................................................................................................................................... 111
CR0E ...................................................................................................................................... 111
CR0F....................................................................................................................................... 111
CR10....................................................................................................................................... 112
CR11....................................................................................................................................... 112
CR12 - CR13............................................................................................................................ 112
CR14....................................................................................................................................... 113
CR15....................................................................................................................................... 113
CR16....................................................................................................................................... 113
SMSC DS – FDC37N869
Page 6
Rev. 11/09/2000

6 Page









FDC37N869TQFP pdf, datenblatt
TQFP
PIN #
82,84
NAME
nRing
Indicator
SYMBOL
nRI1
nRI2
BUFFER
MODE6
I
(Note 1)
DESCRIPTION
Active low Ring Indicator inputs for the serial
port. Handshake signal which notifies the UART
that the telephone ring signal is detected by the
modem. The CPU can monitor the status of nRI
signal by reading bit 6 of Modem Status Register
(MSR). A nRI signal state change from low to
high after the last MSR read will set MSR bit 2 to
a 1. If bit 3 of Interrupt Enable Register is set,
the interrupt is generated when nRI changes
state. Note: Bit 6 of MSR is the complement of
nRI.
TQFP
PIN #
71
72
74
75
59
NAME
nPrinter
Select
Input/FDC
nStep
Pulse
(Note 3)
nInitiate
Output/
FDC
nDirection
Control
(Note 3)
nAutofeed
Output/
FDC
nDensity
Select
(Note 3)
nStrobe
Output/
FDC
nDrive
Select 0
(Note 3)
Busy/
FDC
nMotor On
1
SYMBOL
BUFFER
MODE6
DESCRIPTION
PARALLEL PORT INTERFACE (NOTE 2)
nSLCT
(OD14/OP14)/OD12 This active low output selects the printer.
This is the complement of bit 3 of the
Printer Control Register.
Refer to Parallel Port description for use
of this pin in ECP and EPP mode.
nSTEP
See FDC Pin definition.
nINIT
(OD14/OP14)/OD12 This output is bit 2 of the printer control
register. This is used to initiate the printer
when low.
Refer to Parallel Port description for use
of this pin in ECP and EPP mode.
nDIR
See FDC Pin definition.
nAUTOFD (OD14/OP14)/OD12 This output goes low to cause the printer
to automatically feed one line after each
line is printed. The nAUTOFD output is
the complement of bit 1 of the Printer
Control Register.
Refer to Parallel Port description for use
nDENSEL
of this pin in ECP and EPP mode.
See FDC Pin definition.
nSTROBE (OD14/OP14)/OD12 An active low pulse on this output is used
to strobe the printer data into the printer.
The nSTROBE output is the complement
of bit 0 of the Printer Control Register.
Refer to Parallel Port description for use
of this pin in ECP and EPP mode.
nDS0
See FDC Pin definition.
BUSY
I/OD12
This is a status output from the printer, a
high indicating that the printer is not ready
to receive new data. Bit 7 of the Printer
Status Register is the complement of the
BUSY input. Refer to Parallel Port
description for use of this pin in ECP and
nMTR1
EPP mode.
See FDC Pin definition.
SMSC DS – FDC37N869
Page 12
Rev. 11/09/2000

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