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FDC37C93 Schematic ( PDF Datasheet ) - SMSC Corporation

Teilenummer FDC37C93
Beschreibung Plug and Play Compatible Ultra I/O Controller with Soft Power Management
Hersteller SMSC Corporation
Logo SMSC Corporation Logo 




Gesamt 30 Seiten
FDC37C93 Datasheet, Funktion
FDC37C93xAPM
ADVANCE INFORMATION
Plug and Play Compatible Ultra I/O™ Controller
with Soft Power Management
FEATURES
5 Volt Operation
ISA Plug-and-Play Standard (Version 1.0a)
Compatible Register Set
Soft Power Management, SMI Support
ACPI/Legacy Support
- SCI/SMI Support
- Power Management Timer
- Power Button Override Event
- Either Edge Triggered Interrupts
ACCESS.bus Support
8042 Keyboard Controller
- 2K Program ROM
- 256 Bytes Data RAM
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Timer/Counter
- Port 92 Support
- Fast Gate A20 and Hardware Keyboard
Reset
Real Time Clock
- MC146818 and DS1287 Compatible
- 256 Bytes of Battery Backed CMOS in
Two Banks of 128 Bytes
- 128 Bytes of CMOS RAM Lockable in
4x32 Byte Blocks
- 12 and 24 Hour Time Format
- Binary and BCD Format
- 1 µA Standby Current (typ)
Intelligent Auto Power Management
2.88MB Super I/O Floppy Disk Controller
- Relocatable to 480 Different Addresses
- 13 IRQ Options
- Four DMA Options
- Licensed CMOS 765B Floppy Disk
Controller
- Advanced Digital Data Separator
- Software and Register Compatible with
SMSC's Proprietary 82077AA
Compatible Core
- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power Consumption
- Game Port Select Logic
- Supports Two Floppy Drives Directly
- 24mA AT Bus Drivers
- Low Power CMOS Design
Licensed CMOS 765B Floppy Disk
Controller Core
- Supports Vertical Recording Format
- 16 Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun
Conditions
- 48mA Drivers and Schmitt Trigger Inputs
- DMA Enable Logic
- Data Rate and Drive Control Registers
Enhanced Digital Data Separator
- Low Cost Implementation
- No Filter Components Required
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation Modes
Serial Ports
- Relocatable to 480 Different Addresses






FDC37C93 Datasheet, Funktion
DESCRIPTION OF PIN FUNCTIONS
PIN NO.
NAME
SYMBOL
PROCESSOR/HOST INTERFACE
72:79
41:52
System Data Bus
System Address Bus
SD[0:7]
SA[0:11]
53 Chip Select/SA12 (Active Low)(Note 1, 4)
70 Address Enable (DMA master has bus control)
nCS
AEN
90 I/O Channel Ready
IOCHRDY
80
67:61,
59:54
Reset Drive
Interrupt Requests [1,3:12,14,15]
(Polarity control for IRQ8)
RESET_DRV
IRQ[1,3:12,
14,15]
82,84, DMA Requests
86,88
DRQ[0:3]
81,83,
85,87
89
DMA Acknowledge
Terminal Count
nDACK[0:3]
TC
68 I/O Read
nIOR
69 I/O Write
35 High Speed Clock Out 24/48 MHz
nIOW
HCLK
36 16 MHz Out
16CLK
22 14.318 MHz Clock Input
37 14.318 MHz Clock Output 1
CLOCKI
CLKO1
38 14.318 MHz Clock Output 2
39 14.318 MHz Clock Output 3
CLKO2
CLKO3
POWER PINS
21, 60, +5V Supply Voltage
101, 125,
139
VCC
32
1, 8, 40,
71, 95,
123, 130
Trickle Voltage Input
Ground
VTR
GND
FDD INTERFACE
17 Read Disk Data
nRDATA
BUFFER
TYPE
I/O24
I
I
I
OD24
IS
024/OD24
(Note 0)
O24
I
I
I
I
O20
O8SR
ICLK
O16SR
O8SR
O8SR
IS
6

6 Page









FDC37C93 pdf, datenblatt
Pin Original Alternate Alternate Alternate Buffer
No. Function Function 1 Function 2 Function 3 Type
27 nHDCS2
SA13
-
- I/O24
Default
float
Index
Register
-
GPI/O
-
28 nHDCS3
SA14
-
-
I/O24
float
--
29 IDE2_IRQ
SA15
-
- I float - -
53 nCS/SA 12
-
-
- I input - -
96 GPI/O
IRQ in
-
- I/O4 input GP1 GP10
97 GPI/O
IRQ in
IRQ13
-
I/O4 input GP1 GP11
98 GPI/O
WDT
-
Timer
Output/
IRRX
99
GPI/O
Power LED
-
Output/
IRTX
100 GPI/O
GP
-
Address
Decode
102 GPI/O GP Write
-
Strobe
103
GPI/O
Joy Read
JOYCS
Strobe
104 GPI/O Joy Write
-
Strobe
105 GPI/O
IDE2
8042 P20
Output
Enable
106 GPI/O
Serial
AB_DATA
EEPROM
Data In
107 GPI/O
Serial
AB_CLK
EEPROM
Data Out
108 GPI/O
Serial
EEPROM
Clock
109 GPI/O
Serial
EEPROM
Enable
110 GPI/O 8042 P21
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O4 input
I/O24
I/O4
I/O4
I/O4
I/O4
I/O4
I/O8
/OD8
(EN1)
I/O8
/OD8
(EN1)
I/O4
I/O4
I/O4
input
input
input
input
input
input
input
input
input
input
input
GP1 GP12
GP1 GP13
GP1 GP14
GP1
GP1
GP1
GP2
GP15
GP16
GP17
GP20
GP2 GP21
GP2 GP22
GP2 GP23
GP2 GP24
GP2 GP25
Note 1: At power-up, RD0-RD7, nROMCS and nROMOE function as the XD Bus. To use
RD0-RD7 for functions other than the XD Bus, nROMCS must stay high until
those pins are finished being reprogrammed.
Note 2: These pins are input (high-z) until programmed for second serial port.
Note 3: This is the trickle voltage input pin for the FDC37C93xAPM.
Note 4: These pins cannot be programmed as open drain pins in their original function.
Note: No pins in their original function can be programmed as inverted input or inverted output.
12

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