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PDF FDC37C666GT Data sheet ( Hoja de datos )
| Número de pieza | FDC37C666GT | |
| Descripción | High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers | |
| Fabricantes | ETC | |
| Logotipo |  |
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FDC37C665GT
FDC37C666GT
High-Performance Multi-Mode™
Parallel Port Super I/O Floppy Disk Controllers
FEATURES
• 5 Volt Operation
• Multi-Mode Parallel Port with ChiProtect™
• Floppy Disk Available on Parallel Port Pins
Circuitry
• 2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk
- Standard Mode
- IBM PC/XT®, PC/AT®, and PS/2™
Controller
Compatible Bidirectional Parallel
- Software and Register Compatible to the
Port
82077AA Using SMSC's Proprietary
- Enhanced Mode
Floppy Disk Controller Core
- Enhanced Parallel Port (EPP)
- Supports Vertical Recording Format
Compatible - EPP 1.7 and EPP 1.9
- 100% IBM® Compatibility
(IEEE 1284 Compliant)
- Detects All Overrun and Underrun
- High Speed Mode
Conditions
- Microsoft and Hewlett Packard
- 48 mA Drivers and Schmitt Trigger
Extended Capabilities Port (ECP) IEEE
Inputs
1284 Compliant
- DMA Enable Logic
- Incorporates ChiProtect Circuitry for
- Data Rate and Drive Control Registers
Protection Against Damage Due to
- Swap Drives A and B
Printer Power-On
- Non-Burst Mode DMA Option
- Provides Backdrive Current Protection
- FDC Primary/Secondary Address
- 24 mA Output Drivers
Selection
- Two Parallel Port Interrupt Pins
- 16 Byte Data FIFO
• Serial Ports
- Low Power CMOS 0.8µ Design
• Enhanced Digital Data Separator
- Low Cost Implementation - 24 MHz
Crystal
- No Filter Components Required
- Ease of Test and Use, Lower System
- Two High Speed NS16C550 Compatible
UARTs with Send/Receive 16 Byte
FIFOs
- MIDI Compatible
- Programmable Baud Rate Generator
- Modem Control Circuitry
Cost, and Reduced Board Area
• ISA Host Interface
- 1 Mb/s, 500 Kb/s, 300 Kb/s, 250 Kb/s
• IDE Interface
Data Rates
- On-Chip Decode and Select Logic
- Supports Floppy Disk and Tape Drives
Compatible with IBM PC/XT and PC/AT
- Programmable Precompensation Modes
Embedded Hard Disk Drives
- IDE Primary/Secondary Address
Selection
1 page  
PIN NO.
NAME
DESCRIPTION OF PIN FUNCTIONS
BUFFER
SYMBOL TYPE
DESCRIPTION
HOST PROCESSOR INTERFACE
48-51 Data Bus 0-7
53-56
D0-D7
I/O24
The data bus connection used by the host
microprocessor to transmit data to and from
the FDC37C665GT. These pins are in a
high-impedance state when not in the output
mode.
44 nI/O Read
nIOR
I This active low signal is issued by the host
microprocessor to indicate a read operation.
45 nI/O Write
nIOW
I This active low signal is issued by the host
microprocessor to indicate a write operation.
46 Address Enable AEN
I Active high Address Enable indicates DMA
operations on the host data bus. Used
internally to qualify appropriate address
decodes.
28-34 I/O Address
41-43
A0-A9
I These host address bits determine the I/O
address to be accessed during nIOR and
nIOW cycles. These bits are latched
internally by the leading edge of nIOR and
nIOW.
52 FDC DMA
Request
FDRQ
O24 This active high output is the DMA request
for byte transfers of data to the host. This
signal is cleared on the last byte of the data
transfer by the nDACK signal going low (or
by nIOR going low if nDACK was already
low as in demand mode).
36 nDMA Acknowle- nDACK
dge
I An active low input acknowledging the
request for a DMA transfer of data. This
input enables the DMA read or write
internally.
35 Terminal Count TC
I This signal indicates to the FDC37C665GT
that data transfer is complete. TC is only
accepted when nDACK or nPDACK is low.
In AT and PS/2 model 30 modes, TC is
active high and in PS/2 mode, TC is active
low.
5
5 Page 
PIN NO.
NAME
83 nData Terminal
Ready
DESCRIPTION OF PIN FUNCTIONS
BUFFER
SYMBOL TYPE
DESCRIPTION
nDTR1
O4 Active low Data Terminal Ready output for
primary serial port. Handshake output
signal notifies modem that the UART is
ready to establish data communication link.
This signal can be programmed by writing
to bit 0 of Modem Control Register (MCR).
The hardware reset will reset the nDTR
signal to inactive mode (high). Forced
inactive during loop mode operation.
IDE
Configuration
Control
IDECF
93 nData Terminal nDTR2
Ready
FDC37C666GT (Adapter Mode): IDE
I Configuration Control. During reset active
this input is read and latched to
enable/disable the IDE.
O4 Active low Data Terminal Ready output for
secondary serial port. Handshake output
signal notifies modem that the UART is
ready to establish data communication link.
This signal can be programmed by writing
to bit 0 of Modem Control Register (MCR),
The hardware reset will reset the nDTR
signal to inactive mode (high). Forced
inactive during loop mode operation.
Secondary Serial S2CF1
Port
Configuration
Control 1
89 Transmit Data 2 TXD2
FDC37C666GT (Adapter Mode): Secondary
I Serial Port Configuration Control 1. During
reset active this input is read and latched to
define the address of the Secondary Serial
Port.
O4 Transmitter Serial Data output from
Secondary Serial Port.
FDCCF
I FDC37C666GT (Adapter Mode): Floppy
Disk Configuration. This input is read and
latched during Reset to enable/disable the
Floppy Disk Controller.
11
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