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FB2033 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer FB2033
Beschreibung 8-bit latched/registered/pass-thru Futurebus universal interface transceiver
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 10 Seiten
FB2033 Datasheet, Funktion
Philips Semiconductors
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
Product specification
FB2033
FEATURES
8-bit transceivers
Latched, registered or straight through in either A to B or B to A
path
Drives heavily loaded backplanes with equivalent load
impedances down to 10.
High drive 100mA BTL Open Collector drivers on B-port
Allows incident wave switching in heavily loaded backplane buses
Reduced BTL voltage swing produces less noise and reduces
power consumption
Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
Compatible with IEEE Futurebus+ or proprietary BTL backplanes
Each BTL driver has a dedicated Bus GND for a signal return
Controlled output ramp and multiple GND pins minimize ground
bounce
Glitch-free power up/power down operation
Low ICC current
Tight output skew
Supports live insertion
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH Propagation delay
tPHL
AIn to Bn
tPLH Propagation delay
tPHL
Bn to AOn
COB Output capacitance (B0 – Bn only)
IOL Output current (B0 – Bn only)
AIn to Bn
ICC Supply current
(outputs Low or High)
Bn to AOn (outputs Low)
Bn to AOn (outputs High)
TYPICAL
3.0
3.0
4.3
4.1
6
100
24
45
22
UNIT
ns
ns
pF
mA
mA
ORDERING INFORMATION
PACKAGES
52-pin Plastic Quad Flat Pack (QFP)
NOTE: Thermal mounting or forced air is recommended
PIN CONFIGURATION
COMMERCIAL RANGE
VCC = 5V±10%; Tamb = 0°C to +70°C
FB2033BB
DRAWING
NUMBER
SOT379-1
1995 May 25
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND 1
AO1 2
AI2 3
AO2 4
AI3 5
AO3 6
LOOPBACK 7
AI4 8
AO4 9
AI5 10
AO5 11
AI6 12
LOGIC GND 13
8-Bit Universal Transceiver
FB2033
52-lead PQFP
39 BUS GND
38 B1
37 BUS GND
36 B2
35 BUS GND
34 B3
33 BUS GND
32 B4
31 BUS GND
30 B5
29 BUS GND
28 B6
27 BUS GND
14 15 16 17 18 19 20 21 22 23 24 25 26
1
SG00068
853-1717 15279






FB2033 Datasheet, Funktion
Philips Semiconductors
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
Product specification
FB2033
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
MIN TYP2 MAX
UNIT
IOH
IOFF
VOH
VOL
VIK
II
High level output current
Power-off output current
High-level output voltage
Low-level output voltage
Input clamp voltage
Input current at maximum
input voltage
B0 – Bn
B0 – Bn
AO0 – AOn 4
AO0 – AOn 4
B0 – Bn
Except
B0–Bn
B0 – Bn
Except
B0–Bn
VCC = MAX, VIL = MAX, VIH = MIN, VOH = 1.9V
VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 1.9V
VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA
VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA
VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA
VCC = MIN, VIL = MAX, VIH = MIN, IOL = 4mA
VCC = MIN, II = IIK
VCC = MIN, II = IIK 6
VCC = MIN, II = -18mA
VCC = MAX, VI = 0.0V or 5.5V
2.5
.75
0.5
0.3
2.85
1.0
100
100
0.5
1.15
-0.5
-1.2
±50
µA
µA
V
V
V
µA
IIH High-level input current
IIL Low-level input current
IOZH
IOZL
IOS
Off-state output current
Off-state output current
Short-circuit output
current 3
Except
B0–Bn
B0 – Bn
Except
B0–Bn
B0 – Bn
AO0 – AOn
AO0 – AOn
AO0 – AOn
only
VCC = MAX, VI = 2.7V, Bn = AIn = 0V
VCC = MAX, VI = 1.9V
VCC = MAX, VI = 3.5V 5
VCC = MAX, VI = 0.5V
VCC = MAX, VI = 0.75V
VCC = MAX, VO = 2.7V
VCC = MAX, VO = 0.5V
VCC = MAX, VO = 0.0V
20
µA
100
100 mA
-20
-100
50
-50
µA
µA
µA
-45 -150 mA
ICC Supply current (total)
AIn to Bn
Bn to AOn
Bn to AOn
VCC = MAX, outputs Low or High
VCC = MAX, outputs Low
VCC = MAX, outputs High
24 50
45 75 mA
22 44
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side.
5. For B port input voltage between 3 and 5 volts IIH will be greater than 100µA, but the parts will continue to function normally.
6. B0 – B7 clamps remain active for a minimum of 80ns following a High-to-Low transition.
1995 May 25
6

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