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FIN1216MTD Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer FIN1216MTD
Beschreibung LVDS 21-Bit Serializers/De-Serializers
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 17 Seiten
FIN1216MTD Datasheet, Funktion
October 2003
Revised October 2004
FIN1217 FIN1218
FIN1215 FIN1216
LVDS 21-Bit Serializers/De-Serializers
General Description
The FIN1217 and FIN1215 transform 21-bit wide parallel
LVTTL (Low Voltage TTL) data into 3 serial LVDS (Low
Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 21 bits of input LVTTL data are sampled and trans-
mitted.
The FIN1218 and FIN1216 receive and convert the 3 serial
LVDS data streams back into 21 bits of LVTTL data. Refer
to Table 1 for a matrix summary of the Serializers and De-
serializers available. For the FIN1217, at a transmit clock
frequency of 85 MHz, 21 bits of LVTTL data are transmitted
at a rate of 595 Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and
cable size problems associated with wide and high-speed
TTL interfaces.
Features
s Low power consumption
s 20 MHz to 85 MHz shift clock support
s 50% duty cycle on the clock output of receiver
s ±1V common-mode range around 1.2V
s Narrow bus reduces cable size and cost
s High throughput (up to 1.785 Gbps throughput)
s Up to 595 Mbps per channel
s Internal PLL with no external component
s Compatible with TIA/EIA-644 specification
s Devices are offered in 48-lead TSSOP packages
Ordering Code:
Order Number Package Number
Package Description
FIN1215MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN1216MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN1217MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN1218MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 2004 Fairchild Semiconductor Corporation DS500876
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FIN1216MTD Datasheet, Funktion
Absolute Maximum Ratings(Note 6)
Power Supply Voltage (VCC)
TTL/CMOS Input/Output Voltage
LVDS Input/Output Voltage
LVDS Output Short Circuit Current (IOSD)
Storage Temperature Range (TSTG)
Maximum Junction Temperature (TJ)
Lead Temperature (TL)
(Soldering, 4 seconds)
ESD Rating (HBM, 1.5 k, 100 pF)
LVDS I/O to GND
All Pins (FIN1215, FIN1217 only)
ESD Rating (MM, 0, 200 pF)
(FIN1215, FIN1217 only)
-0.3V to +4.6V
0.5V to +4.6V
-0.3V to +4.6V
Continuous
65°C to +150°C
150°C
260°C
>10.0 kV
>6.5 kV
>400V
Recommended Operating
Conditions
Supply Voltage (VCC)
Operating Temperature (TA)(Note 6)
Maximum Supply Noise Voltage
(VCCNPP)
3.0V to 3.6V
40°C to +85°C
100 mVP-P (Note 7)
Note 6: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
Note 7: 100mV VCC noise should be tested for frequency at least up to
2 MHz. All the specification below should be met under such a noise.
Transmitter DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 8)
Symbol
Parameter
Test Conditions
Transmitter LVTTL Input Characteristics
VIH Input High Voltage
VIL Input Low Voltage
VIK Input Clamp Voltage
IIN Input Current
Transmitter LVDS Output Characteristics (Note 9)
IIK = −18 mA
VIN = 0.4V to 4.6V
VIN = GND
VOD
VOD
VOS
VOS
IOS
Output Differential Voltage
VOD Magnitude Change from Differential LOW-to-HIGH
Offset Voltage
RL = 100 , See Figure 1
Offset Magnitude Change from Differential LOW-to-HIGH
Short Circuit Output Current
VOUT = 0V
IOZ Disabled Output Leakage Current
Transmitter Supply Current
DO = 0V to 4.6V, PwrDn = 0V
ICCWT
21:3 Transmitter Power Supply Current
for Worst Case Pattern (With Load)
(Note 10), (Note 11)
RL = 100 ,
See Figure 3
33.0 MHz
40.0 MHz
65.0 MHz
(85.0 MHz Specification for FIN1217 only)
85.0 MHz
Min
2.0
GND
10.0
250
1.125
Typ
0.79
1.8
0
1.25
3.5
±1.0
28.0
29.0
34.0
39.0
Max
VCC
0.8
1.5
10.0
450
35.0
1.375
5.0
±10.0
46.2
51.7
57.2
62.7
Units
V
V
V
µA
mV
mV
V
mV
mA
µA
mA
ICCPDT Powered Down Supply Current
PwrDn = 0.8V
10.0
55.0
µA
Note 8: All Typical values are at TA = 25°C and with VCC = 3.3V.
Note 9: Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to
ground unless otherwise specified (except VOD and VOD).
Note 10: The power supply current for both transmitter and receiver can be different with the number of active I/O channels.
Note 11: The 16-grayscale test pattern tests device power consumption for a typicalLCD display pattern. The test pattern approximates signal switching
needed to produce groups of 16 vertical strips across the display.
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FIN1216MTD pdf, datenblatt
AC Loading and Waveforms (Continued)
FIGURE 8. Receiver Setup/Hold and HIGH/LOW Times
FIGURE 9. Transmitter Clock In to Clock Out Delay (Rising Edge Strobe)
FIGURE 10. Receiver Clock In to Clock Out Delay (Falling Edge Strobe)
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