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FIN1102 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer FIN1102
Beschreibung LVDS 2 Port High Speed Repeater
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 5 Seiten
FIN1102 Datasheet, Funktion
January 2002
Revised February 2002
FIN1102
LVDS 2 Port High Speed Repeater
General Description
This 2 port repeater is designed for high speed intercon-
nects utilizing Low Voltage Differential Signaling (LVDS)
technology. The FIN1102 accepts and outputs LVDS levels
with a typical differential output swing of 330 mV which pro-
vides low EMI at ultra low power dissipation even at high
frequencies. The FIN1102 provides a VBB reference for AC
coupling on the inputs. In addition the FIN1102 can also
directly accept LVPECL, HSTL, and SSTL-2 for translation
to LVDS.
Features
s Greater than 800 Mbps full differential path
s 3.3V power supply operation
s 3.5 ps maximum random jitter and 135 ps maximum
deterministic jitter
s Wide rail-to-rail common mode range
s LVDS receiver inputs accept LVPECL, HSTL, and
SSTL-2 directly
s Ultra low power consumption
s 20 ps typical channel-to-channel skew
s Power off protection
s > 7 kV HBM ESD Protection
s Meets or exceeds the TIA/EIA-644-A LVDS standard
s 14-lead TSSOP package saves space
s Open circuit fail safe protection
s VBB reference output
Ordering Code:
Order Number Package Number
Package Description
FIN1102MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pin Descriptions
Connection Diagram
Pin Name
Description
RIN1+, RIN2+
Non-inverting LVDS Input
RIN1, RIN2
Inverting LVDS Input
DOUT1+, DOUT2+ Non-inverting Driver Output
DOUT1, DOUT2Inverting Driver Output
EN Driver Enable Pin for All Output
VCC
GND
Power Supply
Ground
VBB Reference Voltage Output
Function Table
Inputs
EN
DIN+
DIN
H HL
H LH
H Fail Safe Case
L XX
H = HIGH Logic Level
L = LOW Logic Level
X = Don't Care
Z = High Impedance
Outputs
DOUT+
DOUT
HL
LH
HL
ZZ
Functional Diagram
© 2002 Fairchild Semiconductor Corporation DS500657
www.fairchildsemi.com





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