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FIN1022M Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer FIN1022M
Beschreibung 2 X 2 LVDS High Speed Crosspoint Switch
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 10 Seiten
FIN1022M Datasheet, Funktion
September 2001
Revised December 2001
FIN1022
2 X 2 LVDS High Speed Crosspoint Switch
General Description
This non-blocking 2x2 crosspoint switch has a fully differ-
ential input to output data path for low noise generation and
low pulse width distortion. The device can be used as a
high speed crosspoint switch, 2:1 multiplexer, 1:2 demulti-
plexer or 1:2 signal splitter. The inputs can directly interface
with LVDS and LVPECL levels.
Features
s Low jitter, 800 Mbps full differential data path
s Worst case jitter of 190ps
with PRBS = 223 1 data pattern at 800 Mbps
s Rail-to-rail common mode range is 0.5V to 3.25V
s Worst case power dissipation is less than 126 mW
s Open-circuit fail safe protection
s Fast switch time of 1.1 ns typical
s 35 ps typical pin channel to channel skew
s 3.3V power supply operation
s Non-blocking switch
s LVDS receiver inputs accept LVPECL signals directly
s 7.5 kV HBM ESD protection
s 16-lead SOIC package and TSSOP package
s Inter-operates with TIA/EIA 644-1995 specification
s See the Fairchild Interface Solutions web page for cross
reference information:
www.fairchildsemi.com/products/interface/lvds.html
Ordering Code:
Order Number Package Number
Package Description
FIN1022M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
FIN1022MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500653
www.fairchildsemi.com






FIN1022M Datasheet, Funktion
Required Specifications (Continued)
FIGURE 3. LVDS Driver DC Test Circuit
Note A: All input pulses have frequency = 50 MHz, tR or tF = 500 ps
Note B: CL includes all probe and jig capacitances
FIGURE 4. LVDS Input to LVDS Driver Propagation
Delay and Transition Time Circuit
FIGURE 5. LVDS Input to LVDS Output AC Waveforms
FIGURE 6. LVTTL Input to LVDS Driver Propagation
Delay and Transition Time Test Circuit
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