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M2082 Schematic ( PDF Datasheet ) - Integrated Circuit Solution Inc

Teilenummer M2082
Beschreibung VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
Hersteller Integrated Circuit Solution Inc
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Gesamt 14 Seiten
M2082 Datasheet, Funktion
Integrated
Circuit
Systems, Inc.
P r e l i m i n a r y I n f o r m a t i o n M2080/81/82
M2085/86/87
VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M2080/81/82 and M2085/86/87 are VCSO (Voltage
Controlled SAW Oscillator) based
clock PLLs designed for FEC clock
ratio translation in 10Gb optical
systems such as OC-192 or 10GbE.
They support FEC (Forward Error
Correction) clock multiplication
ratios, both forward (mapping) and
inverse (de-mapping). Multiplication ratios are
pin-selected from pre-programming look-up tables.
FEATURES
Integrated SAW delay line; Output of 15 to 700 MHz *
Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
LVPECL clock output (CML and LVDS options available)
Pin-selectable PLL divider ratios support FEC ratios
• M2080/85: OTU1 (255/238) and OTU2 (255/237) Mapping
• M2081/86: OTU1 (238/255) or OTU2 (237/255) De-mapping
• M2082/87: OTU1 (238/255) and OTU2 (237/255) De-mapping
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Options for Hitless Switching (HS) with or without
Phase Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30 M 2 0 8 0
31
32 S e r i e s
16
15
14
33 13
34 ( T o p V i e w ) 12
35 11
36 10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M2081-11-622.0800 FEC De-Map Ratios
FEC De-Map
PLL Ratio
Mfec / Rfec
Base Input Rate 1
(MHz)
Output Clock
(either output)
MHz
1/1
237/255
238/255
622.0800
666.5143
669.3266
622.08
or
155.52
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be the base frequency shown
divided by “Mfin” (as shown in Tables 3 and 4 on pg. 3).
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
M2080 Series
MUX
0 Rfec
Div
1
PLL
Phase
Detector
0
1
Auto
Ref Sel
LOL Phase
Detector
Mfec Div
2
FEC_SEL1:0
2
FIN_SEL1:0
3
P_SEL2:0
Mfec / Rfec Divider
LUT
Mfin Divider
LUT
Loop Filter
Mfin Divider
(1, 4, 8, 32 or
1, 4, 8, 16)
VCSO
P Divider
(1, 4, 8, 32 or TriState)
Tri-state
P Divider
LUT
Figure 2: Simplified Block Diagram
LOL
FOUT
nFOUT
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
Revised 30Jul2004
M2080/81/82 VCSO FEC PLL with AutoSwitch for SONET/OTN
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400






M2082 Datasheet, Funktion
Integrated
Circuit
Systems, Inc.
M2080/81/82, M2085/86/87
VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
Preliminary Information
The relationship between the nominal VCSO center
frequency (Fvcso), the Mfin divider, the Mfec divider,
the Rfec divider, and the input reference frequency (Fin)
is:
Fvcso
=
Fin
×
Mfin
×
-M-----f--e----c-
Rfec
The Mfec, Rfec, and Mfin dividers can be set by pin
configuration using the input pins FEC_SEL1, FEC_SEL0,
FIN_SEL1, and FIN_SEL0.
Post-PLL Divider
The M2080/81/82 and M2085/86/87 also feature a
post-PLL (P) divider.
Through use of the P divider, the device’s output
frequency (Fout) can be that of the VCSO (such as
622.08MHz) or the VCSO frequency divided by 4, 8 or 32
(common optical reference clocks in SONET and SDH
systems).
The P_SEL2:0 pins select the value for the P divider. (See
Table 8 on pg. 4.)
Accounting for the P divider, the complete relationship
between the input clock reference frequency (Fin) and
output clock frequency (Fout) is defined as:
Fout
=
---F---v---c---s---o----
P
=
Fin ×
--M-----Rf--i--nf--e--×-c----×M-----fP--e---c---
Due to the narrow tuning range of the VCSO (+120ppm
guaranteed), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
Loss of Lock Indicator (LOL) Output Pin
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives LOL to logic 0. Under
circumstances when the VCSO cannot fully phase lock
to the input (as measured by a greater than 4 ns
discrepancy between the feedback and reference clock
rising edges at the LOL Phase Detector) the LOL output
goes to logic 1. The LOL pin will return back to logic 0
when the phase detector error is less than 2 ns. The
loss of lock indicator is a low current LVCMOS output.
Guidelines for Using LOL
In a given application, the magnitude of peak-to-peak
jitter at the phase detector will usually increase as the
Rfec divider is increased. If the LOL pin will be used to
detect an unusual clock condition, or a clock fault, the
FEC_SEL1:0 pins should be set to provide a phase
detector frequency of 5MHz or greater (the phase
detector frequency is equal to Fin divided by the Rfec
divider). Otherwise, false LOL indications may result. A
phase detector frequency of 10MHz or greater is
desirable when reference jitter is over 500ps, or when
the device is used within a noisy system environment.
LOL should not be used when the device is used in a
loop timing application.
TriState
The TriState feature puts the LVPECL output driver into
a high impedance state, effectively disconnecting the
driver from the FOUT and nFOUT pins of the device. In
TriState, the M208x Series is not driving the output
clock net with a defined logic level. The impedance of
the clock net is then set to 50by the external circuit
resistors. The 50impedance level of the LVPECL
TriState allows manufacturing In-circuit Test to drive the
clock net with an external LVPECL source to validate
the integrity of clock net and the clock load.
Any unused output (single-ended or differential) should
be left unconnected (floating) in system application.
This minimizes output switching current and therefore
minimizes noise modulation of the VCSO.
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
6 of 14
Revised 30Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

6 Page









M2082 pdf, datenblatt
Integrated
Circuit
Systems, Inc.
M2080/81/82, M2085/86/87
VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
Preliminary Information
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz,
LVPECL outputs terminated with 50to VCC - 2V
Symbol Parameter
Min Typ Max Unit Conditions
FIN Input Frequency
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
10
700 MHz
FOUT
APR
PLL Loop
Constants 1
KVCO
RIN
Output Frequency
FOUT, nFOUT
VCSO Absolute
Pull-Range
VCO Gain
Internal Loop Resistor
Commercial
Industrial
Wide Bandwidth
Narrow Bandwidth
15
±120
±50
±200
±150
800
100
2100
700 MHz
ppm
ppm
kHz/V
k
k
Phase Noise
and Jitter
BWVCSO
Φn
VCSO Bandwidth
Single Side Band
Phase Noise
@622.08MHz
J(t) Jitter (rms)
@622.08MHz
odc Output Duty Cycle 2
FOUT, nFOUT
tR Output Rise Time 2
tF Output Fall Time 2
1kHz Offset
10kHz Offset
100kHz Offset
12kHz to 20MHz
50kHz to 80MHz
P = 4, 8, or 32
P=1
FOUT, nFOUT
700
-73
-103
-126
0.25
0.25
45 50
40 50
200 450
200 450
kHz
dBc/Hz Fin=19.44 or
dBc/Hz
38.88 MHz
Mfin=32 or 16,
dBc/Hz Mfec=Rfec
0.5 ps
0.5 ps
55 %
60 %
500 ps
20% to 80%
500 ps 20% to 80%
Table 15: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 11, Example Values for Loop Filter External Components, on pg. 9.
Note 2: See Parameter Measurement Information on pg. 12.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Output Duty Cycle
nFOUT
20%
Clock Output
80%
tR
80%
VP-P
20%
tF
Figure 6: Output Rise and Fall Time
FOUT
odc =
tPW
tPERIOD
tPW
(Output Pulse Width)
tPERIOD
Figure 7: Output Duty Cycle
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
12 of 14
Revised 30Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

12 Page





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