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Teilenummer | LV1100 |
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Beschreibung | Digital Surround Audio Signal-Processing IC | |
Hersteller | Sanyo Semicon Device | |
Logo | ||
Gesamt 10 Seiten Ordering number : EN5506
Bi-CMOS LSI
LV1100
Digital Surround Audio Signal-Processing IC
Overview
The LV1100 is an audio signal-processing Bi-CMOS LSI
that integrates input and output filters, a delay line (built-
in memory), and a delay/reverb function with a maximum
delay of 120 ms on a single chip. It also provides built-in
fixed matrix (L+R, L–R) and front mixing (with level and
phase switching) functions. A full complement of
surround modes can be easily implemented by combining
these functions.
Functions and Features
• Input switching (L+R, L–R, IN–A)
• On-chip memory (12K SRAM)
• Front adder (+3 dB, 0 dB, –3 dB, -∞)
• Input and output filters
• Input filter –7 kHz low-pass filter
• Output filter –5 kHz low-pass filter: switchable with a
3 kHz low-pass filter
• On-chip VDD circuit
• Input and output muting function
• A simulated surround system can be easily implemented
with only one chip.
• ADM A/D and D/A converters
• Variable delay times
– Short mode; Maximum delay: 60 ms. Delay time
selectable from six delay times in 10-ms steps.
– Long mode; Maximum delay: 120 ms. Delay time
selectable from six delay times in 20-ms steps.
Package Dimensions
unit: mm
3067-DIP24S
[LV1100]
SANYO: DIP24S
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VCC max
Pd max
Topr
Tstg
Ta ≤ 70°C
Allowable Operating Ranges at Ta = 25°C
Parameter
Recommended supply voltage
Operating supply voltage range
Symbol
VCC
VCC opg
Conditions
Conditions
Ratings
12
420
–25 to +70
–40 to +125
Unit
V
mW
°C
°C
Ratings
9
8 to 10
Unit
V
V
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
83196HA (OT) No. 5506-1/10
LV1100
Delay Time Data (D6 to D8)
D6 D7 D8
CLK FAST
CLK SLOW
LLL
10 ms
20 ms
L LH
20 ms
40 ms
LHL
30 ms
60 ms
L HH
40 ms
80 ms
HL L
50 ms
100 ms
HLH
60 ms
120 ms
Note: D6, D7, and D8 must not be used for any purposes other than the above commands.
L
D9 SYSTEM MUTE ON
D10 CLK FAST
Control Data Format
H
SYSTEM MUTE OFF
CLK SLOW
• Data is read in on the rising edge of the clock.
• The control data consists of 12 bits.
• The input data is latched on the rising edge of the enable signal.
• The clock and enable signals must be held high when not being used to control the LV1100.
• Command interval time
The timing of intervals between enable signals must meet the conditions shown in the figure.
Notes on Mode Control (System Mute Usage)
1 When power is first applied, after the IC is fully operating (about 2 seconds after power is applied) applications must
send commands that turn the system muting off and then on again.
2 Applications must perform system muting on/off operations when switching the delay time or clock fast/slow
settings. After sending a system muting on command along with the new data, send the new data again, this time with
a system muting off command.
Note: By performing the operations described in items 1 and 2 here, the memory contents are initialized, thus preventing incorrect operation.
No. 5506-6/10
6 Page | ||
Seiten | Gesamt 10 Seiten | |
PDF Download | [ LV1100 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
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