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39LF020 Schematic ( PDF Datasheet ) - Silicon Storage Technology Inc

Teilenummer 39LF020
Beschreibung 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
Hersteller Silicon Storage Technology Inc
Logo Silicon Storage Technology  Inc Logo 




Gesamt 24 Seiten
39LF020 Datasheet, Funktion
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories
FEATURES:
Data Sheet
• Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8
• Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF512/010/020/040
– 2.7-3.6V for SST39VF512/010/020/040
Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
Low Power Consumption:
Active Current: 10 mA (typical)
Standby Current: 1 µA (typical)
Sector-Erase Capability
Uniform 4 KByte sectors
Fast Read Access Time:
45 ns for SST39LF512/010/020/040
55 ns for SST39LF020/040
70 and 90 ns for SST39VF512/010/020/040
Latched Address and Data
Fast Erase and Byte-Program:
Sector-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Byte-Program Time: 14 µs (typical)
Chip Rewrite Time:
1 second (typical) for SST39LF/VF512
2 seconds (typical) for SST39LF/VF010
4 seconds (typical) for SST39LF/VF020
8 seconds (typical) for SST39LF/VF040
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bit
Data# Polling
CMOS I/O Compatibility
JEDEC Standard
Flash EEPROM Pinouts and command sets
Packages Available
32-lead PLCC
32-lead TSOP (8mm x 14mm)
48-ball TFBGA (6mm x 8mm) for 1 Mbit
PRODUCT DESCRIPTION
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 are 64K x8, 128K x8, 256K x8 and 5124K x8
CMOS Multi-Purpose Flash (MPF) manufactured with
SSTs proprietary, high performance CMOS SuperFlash
technology. The split-gate cell design and thick oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39LF512/
010/020/040 devices write (Program or Erase) with a 3.0-
3.6V power supply. The SST39VF512/010/020/040
devices write with a 2.7-3.6V power supply. The devices
conform to JEDEC standard pinouts for x8 memories.
Featuring high performance Byte-Program, the
SST39LF512/010/020/040 and SST39VF512/010/020/
040 devices provide a maximum Byte-Program time of 20
µsec. These devices use Toggle Bit or Data# Polling to indi-
cate the completion of Program operation. To protect
against inadvertent write, they have on-chip hardware and
Software Data Protection schemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, they
are offered with a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices are suited for applications that require
convenient and economical updating of program, configu-
ration, or data memory. For all system applications, they
significantly improves performance and reliability, while low-
ering power consumption. They inherently use less energy
during Erase and Program than alternative flash technolo-
gies. The total energy consumed is a function of the
applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time, the
total energy consumed during any Erase or Program oper-
ation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet surface mount requirements, the SST39LF512/
010/020/040 and SST39VF512/010/020/040 devices are
offered in 32-lead PLCC and 32-lead TSOP packages. The
39LF/VF010 is also offered in a 48-ball TFBGA package.
See Figures 1 and 2 for pinouts.
©2001 Silicon Storage Technology, Inc.
S71150-03-000 6/01
395
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.






39LF020 Datasheet, Funktion
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TABLE 2: PIN DESCRIPTION
Symbol
AMS1-A0
Pin Name
Address Inputs
Functions
To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the
sector. During Block-Erase AMS-A16 address lines will select the block.
DQ7-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
VDD
Power Supply
To provide power supply voltage: 3.0-3.6V for SST39LF512/010/020/040
2.7-3.6V for SST39VF512/010/020/040
VSS Ground
NC
No Connection
Unconnected pins.
1. AMS = Most significant address
AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040
T2.1 395
TABLE 3: OPERATION MODES SELECTION
Mode
Read
Program
Erase
CE#
VIL
VIL
VIL
OE#
VIL
VIH
VIH
Standby
Write Inhibit
Product Identification
Software Mode
VIH
X
X
VIL
1. X can be VIL or VIH, but no other value.
X
VIL
X
VIL
WE#
VIH
VIL
VIL
DQ
DOUT
DIN
X1
X High Z
X High Z/ DOUT
VIH High Z/ DOUT
VIH
Address
AIN
AIN
Sector address,
XXH for Chip-Erase
X
X
X
See Table 4
T3.4 395
©2001 Silicon Storage Technology, Inc.
6
S71150-03-000 6/01 395

6 Page









39LF020 pdf, datenblatt
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
ADDRESS AMS-0
CE#
OE#
TOEH
TCE
TOE
WE#
DQ6
Note:
TWO READ CYCLES
AMS = Most significant address
WITH SAME OUTPUTS
AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010,
A17 for SST39LF/VF020 and A18 for SST39LF/VF040
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
TOES
395 ILL F07.0
ADDRESS AMS-0
CE#
5555
SIX-BYTE CODE FOR SECTOR-ERASE
2AAA
5555
5555
2AAA
SAX
TSE
OE#
WE#
TWP
DQ7-0
AA 55
80 AA 55
30
FIGURE
SW0
SW1
SW2
SW3
SW4
SW5
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
334 ILL F08.0
interchageable as long as minmum timings are met. (See Table 10)
SAX = Sector Address
AMS = Most significant address
AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
12
S71150-03-000 6/01 395

12 Page





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