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37LV128-TSN Schematic ( PDF Datasheet ) - Microchip Technology

Teilenummer 37LV128-TSN
Beschreibung 36K/ 64K/ and 128K Serial EPROM Family
Hersteller Microchip Technology
Logo Microchip Technology Logo 




Gesamt 12 Seiten
37LV128-TSN Datasheet, Funktion
37LV36/65/128
36K, 64K, and 128K Serial EPROM Family
FEATURES
• Operationally equivalent to Xilinx® XC1700 family
• Wide voltage range 3.0 V to 6.0 V
• Maximum read current 10 mA at 5.0 V
• Standby current 100 µA typical
• Industry standard Synchronous Serial Interface/
1 bit per rising edge of clock
• Full Static Operation
• Sequential Read/Program
• Cascadable Output Enable
• 10 MHz Maximum Clock Rate @ 5.0 Vdc
• Programmable Polarity on Hardware Reset
• Programming with industry standard EPROM pro-
grammers
• Electrostatic discharge protection > 4,000 volts
• 8-pin PDIP/SOIC and 20-pin PLCC packages
• Data Retention > 200 years
• Temperature ranges:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 37LV36/65/128 is a
family of Serial OTP EPROM devices organized inter-
nally in a x32 configuration. The family also features a
cascadable option for increased memory storage
where needed. The 37LV36/65/128 is suitable for
many applications in which look-up table information
storage is desirable and provides full static operation in
the 3.0V to 6.0V VCC range. The devices also support
the industry standard serial interface to the popular
RAM-based Field Programmable Gate Arrays (FPGA).
Advanced CMOS technology makes this an ideal boot-
strap solution for today's high speed SRAM-based
FPGAs. The 37LV36/65/128 family is available in the
standard 8-pin plastic DIP, 8-pin SOIC and 20-pin
PLCC packages.
Device Bits Programming Word
37LV36
37LV65
37LV128
36,288
65,536
131,072
1134 x 32
2048 x 32
4096 x 32
Xilinx is a registered trademark of Xilinx Corporation.
PACKAGE TYPES
PDIP
DATA 1
CLK 2
RESET/OE 3
CE 4
8 VCC
7 VPP
6 CEO
5 VSS
SOIC
DATA
CLK
RESET/OE
CE
PLCC
18
27
36
45
DATA VCC
VCC
VPP
CEO
VSS
CLK 4
5
RESET/OE 6
7
CE 8
18
17 VPP
16
15
14 CEO
Vss
BLOCK DIAGRAM
CE
RESET/OE
CEO
ADDRESS EPROM
Counter ARRAY
CLK
OE
DATA
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS21109E-page 1






37LV128-TSN Datasheet, Funktion
37LV36/65/128
TABLE 11-3: PIN ASSIGNMENTS IN THE PROGRAMMING MODE
DIP/SOIC
Pin
PLCC Pin
Name
I/O
Description
1
2
DATA
I/O The rising edge of the clock shifts a data word in or out of the
EPROM one bit at a time.
2 4 CLK I Clock Input. Used to increment the internal address/word
counter for reading and programming operation.
3 6 RESET/OE I The rising edge of CLK shifts a data word into the EPROM
when CE and OE are HIGH; it shifts a data word out of the
EPROM when CE is LOW and OE is HIGH. The address/
word counter is incremented on the rising edge of CLK while
CE is held HIGH and OE is held LOW.
Note 1: Any modified polarity of the RESET/OE pin is
ignored in the programming mode.
4 8 CE I The rising edge of CLK shifts a data word into the EPROM
when CE and OE are HIGH; it shifts a data word out of the
EPROM when CE is LOW and OE is HIGH. The address/
word counter is incremented on the rising edge of CLK while
CE is held HIGH and OE is held LOW.
5 10 VSS
Ground pin.
6 14 CEO O The polarity of the RESET/OE pin can be read by sensing the
CEO pin.
Note 1: The polarity of the RESET/OE pin is ignored while in
the Programming Mode. In final verification, this pin
must be monitored to go LOW one clock cycle after
the last data bit has been read.
7 17 VPP
Programming Voltage Supply. Programming Mode is entered
by holding CE and OE HIGH and VPP at VPP1 for two rising
clock edges and then lowering VPP to VPP2 for one more ris-
ing clock edge. A word is programmed by strobing the device
with VPP for the duration TPGM. VPP must be tied to VCC for
normal read operation.
8 20 VCC
+5 V power supply input.
DS21109E-page 6
© 1996 Microchip Technology Inc.

6 Page









37LV128-TSN pdf, datenblatt
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9/3/96
All rights reserved. © 1996, Microchip Technology Incorporated, USA. 9/96
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21109E-page 12
© 1996 Microchip Technology Inc.

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