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PDF CXK77V3211Q Data sheet ( Hoja de datos )
| Número de pieza | CXK77V3211Q | |
| Descripción | 32768-word by 32-bit High Speed Synchronous Static RAM | |
| Fabricantes | Sony Corporation | |
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CXK77V3211Q -12/14
32768-word by 32-bit High Speed Synchronous Static RAM
For the availability of this product, please contact the sales office.
Description
The CXK77V3211Q is a 32K × 32 high performance
synchronous SRAM with a 2-bit burst counter and
output register. All synchronous inputs pass through
register controlled by a positive-edge-triggered
single clock input (CLK). The synchronous inputs
include all addresses, all data inputs, chip enable
(CE), two additional chip enables for easy depth
expansion (CE2, CE2), burst control inputs (ADSC,
ADSP, ADV), four individual byte write enables
(BW1, BW2, BW3, BW4), one byte write enable
(BWE), and global write enable (SGW).
Asynchronous inputs include the output enable
(OE) and power down control (ZZ). Two mode
control pins (LBO, FT) define four different operation
modes: Linear/Interleaved burst sequence and
Flow-Thru/Pipelined operations.
WRITE cycles can be from one to four bytes wide
as controlled by BW1 through BW4 and BWE or
SGW. The output register is included on-chip and
controlled by clock, it can be activated by connecting
FT to high for high speed pipeline operation.
Burst operation can be initiated with either address
status processor (ADSP) or address status
controller (ADSC) input pins. Subsequent burst
addresses can be internally generated as controlled
by the burst advance pin (ADV). Burst order
sequence can be controlled by connecting LBO to
high for Interleaved burst order (i486/Pentium™) or
by connecting LBO to low for Linear burst order.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed
WRITE cycles. Individual byte enables allow
individual bytes to be written. WRITE pass through
makes written data immediately available at the
output register during READ cycle following a
WRITE as controlled by OE.
The CXK77V3211Q operates from a +3.3V power
supply and all inputs and outputs are LVTTL
compatible. The device is ideally suited for i486 and
Pentium™ systems and those systems which
benefit from a very wide data bus.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• Fast address access times and High frequency
operation
Symbol
-12
-14
Flow-through
Access Cycle
12ns 60MHz
14ns 50MHz
Pipeline
Access Cycle
7ns 75MHz
8ns 66MHz
• 5V tolerant inputs except I/O pins
• A FT pin for pipelined or flow-thru architecture
• A LBO mode pin as burst control pin
(i486/Pentium™ and Linear burst sequence)
•
Single
+3.3V
+10%
– 5%
power supply
• Common data inputs and data outputs
• All inputs and outputs are LVTTL compatible
• Four Individual BYTE WRITE enables, GLOBAL
WRITE and BYTE WRITE ENABLE
• Three Chip Enables for simple depth expansion
• One cycle output disable for both pipelined and
flow-thru operation
• Internal input registers for address, data and
control signals
• Self-timed WRITE cycle
• Write pass through capability
• High 30pF output drive capability at rated access
time
• A ZZ pin for powerdown
• 100-lead QFP package for high density, high
speed operation
i486/Pentium is a trademark of Intel Corp.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95721-PS
1 page  
Interleaved Burst Sequence Table
Operation
First access, latch external address
Second access (first burst address)
Third access (second burst address)
Fourth access (third burst address)
A14 to A2
A14 to A2
latched A14 to A2
latched A14 to A2
latched A14 to A2
Address used
A1
A1
latched A1
latched A1
latched A1
CXK77V3211Q
A0
A0
latched A0
latched A0
latched A0
Interleaved Burst Address Table
First address Second address
X...X00
X...X01
X...X01
X...X00
X...X10
X...X11
X...X11
X...X10
Third address
X...X10
X...X11
X...X00
X...X01
Fourth address
X...X11
X...X10
X...X01
X...X00
Linear Burst Address Table
First address Second address
X...X00
X...X01
X...X01
X...X10
X...X10
X...X11
X...X11
X...X00
Third address
X...X10
X...X11
X...X00
X...X01
Fourth address
X...X11
X...X00
X...X01
X...X10
Pass-Through Truth Table
Previous cycle
Present cycle
Next cycle
Operation
BWs
Operation
CE BWs OE
Operation
Initial WRITE cycle, all bytes
Address = A (n – 1),
data = D (n – 1)
All L
Initial READ cycle
Register A (n), Q = D (n – 1)
L
H
L Read D (n)
Initial WRITE cycle, all bytes
Address = A (n – 1),
data = D (n – 1)
All L
No new cycle
Q = D (n – 1)
H
H
L
No carryover from
previous cycle
Initial WRITE cycle, all bytes
Address = A (n – 1),
data = D (n – 1)
All L
No new cycle
Q = HIGH-Z
H
H
H
No carryover from
previous cycle
Initial WRITE cycle, one byte
Address = A (n – 1),
data = D (n – 1)
One L
No new cycle
Q = D (n – 1) for one byte
H
H
L
No carryover from
previous cycle
Note) Previous cycle may be either BURST or NONBURST cycle.
–5–
5 Page 
CXK77V3211Q
Read Timing (Pipeline)
CLK
ADSP
ADSC
ADDR.
BW1 to BW4
CE
(∗2)
ADV
OE
Q
tKC
tKH tKL
tS tH
tS tH
tS tH
A1
tS tH
A2
A3 A4
Burst continued with
new base address
tS tH
Deselect cycle
tS tH
ADV suspends burst
High-Z
tOE
tLZ
tKQ
tOHZ
Q (A1)
Single READ
tOLZ
tKQ
tKQX
Q (A2)
Q
(A2 + 1)
(∗1)
Q (A2 + 2)
Q
(A2 + 3)
Q (A2)
(∗3)
tHZ
Q
(A2 + 1)
Burst READ
Burst wrap around
to its initial state.
DON'T CARE
UNDEFINED
∗1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address
following A2.
∗2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is
HIGH. When CE is HIGH, CE2 is HIGH and CE is LOW.
∗3 On deselect cycle, Q is tri-stated immediately on the same cycle CE is LOW.
– 11 –
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CXK77V3211Q.PDF ] | |
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