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PDF CXK5T8512TN-12LLX Data sheet ( Hoja de datos )
| Número de pieza | CXK5T8512TN-12LLX | |
| Descripción | 65536-word X 8-bit High Speed CMOS Static RAM | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXK5T8512TM/TN -10LLX/12LLX
65536-word × 8-bit High Speed CMOS Static RAM Preliminary
For the availability of this product, please contact the sales office.
Description
The CXK5T8512TM/TN is a high speed CMOS
static RAM organized as 65536-words by 8-bits.
Special feature are low power consumption and
high speed.
The CXK5T8512TM/TN is a suitable RAM for
portable equipment with battery back up.
CXK5T8512TM
32 pin TSOP (Plastic)
CXK5T8512TN
32 pin TSOP (Plastic)
Features
• Extended operating temperature range:
–25 to +85°C
• Wide supply voltage range operation: 2.7 to 3.6V
• Fast access time:
(Access time)
3.0V operation
CXK5T8512TM/TN-10LLX 100ns (Max.)
CXK5T8512TM/TN-12LLX 120ns (Max.)
3.3V operation
CXK5T8512TM/TN-10LLX 85ns (Max.)
CXK5T8512TM/TN-12LLX 100ns (Max.)
• Low standby current:
14µA (Max.)
• Low data retention current: 12µA (Max.)
• Low power data retention: 2.0V (Min.)
• Package line-up
CXK5T8512TM
8mm × 20mm 32 pin TSOP package
CXK5T8512TN
8mm × 13.4mm 32 pin TSOP package
Function
65536-word × 8-bit static RAM
Block Diagram
A15
A13
A8
A11
A9
A7
A6
A5
A14
A12
A4
A3
A10
A0
A2
A1
OE
WE
CE1
CE2
Buffer
Buffer
Buffer
Row
Decoder
Memory
Matrix
1024 × 512
I/O Gate
Column
Decoder
I/O Buffer
I/O1 I/O8
VCC
GND
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
PE96727-PS
1 page  
CXK5T8512TM/TN
• Read cycle (WE = “H”)
VCC = 2.7 to 3.6V
VCC = 3.3V ± 0.3V
Item
Symbol -10LLX
-12LLX
-10LLX
-12LLX Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read cycle time
tRC 100 — 120 — 85 — 100 — ns
Address access time
tAA — 100 — 120 — 85 — 100 ns
Chip enable access time (CE1)
tCO1 — 100 — 120 — 85 — 100 ns
Chip enable access time (CE2)
tCO2 — 100 — 120 — 85 — 100 ns
Output enable to output valid
tOE — 50 — 60 — 40 — 50 ns
Output hold from address change
tOH 10 — 10 — 10 — 10 — ns
Chip enable to output in low Z
(CE1, CE2)
tLZ1
tLZ2
10 — 10 — 10 — 10 — ns
Output enable to output in low Z (OE) tOLZ
5 — 5 — 5 — 5 — ns
Chip disable to output in high Z
(CE1, CE2)
tHZ1∗1
tHZ2∗1
—
40
—
40
—
35
—
40 ns
Output disable to output in high Z (OE) tOHZ∗1 — 35 — 35 — 30 — 35 ns
∗1 tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
• Write cycle
VCC = 2.7 to 3.6V
VCC = 3.3V ± 0.3V
Item
Symbol -10LLX
-12LLX
-10LLX
-12LLX Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Write cycle time
tWC 100 — 120 — 85 — 100 — ns
Address valid to end of write
tAW 80 — 100 — 70 — 80 — ns
Chip enable to end of write
tCW 80 — 100 — 70 — 80 — ns
Data to write time overlap
tDW 40 — 50 — 35 — 40 — ns
Data hold from write time
tDH 0 — 0 — 0 — 0 — ns
Write pulse width
tWP 70 — 70 — 60 — 70 — ns
Address setup time
tAS 0 — 0 — 0 — 0 — ns
Write recovery time (WE)
tWR 5 — 5 — 5 — 5 — ns
Write recovery time (CE1, CE2)
tWR1
5 — 5 — 5 — 5 — ns
Output active from end of write
Write to output in high Z
tOW 5 — 5 — 5 — 5 — ns
tWHZ∗2 — 40 — 40 — 35 — 40 ns
∗2 tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
–5–
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CXK5T8512TN-12LLX.PDF ] | |
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