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PDF CXK5B18120TM- Data sheet ( Hoja de datos )

Número de pieza CXK5B18120TM-
Descripción 65536-word x 18-bit High Speed Bi-CMOS Static RAM
Fabricantes Sony Corporation 
Logotipo Sony Corporation Logotipo



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CXK5B18120TM -12
65536-word × 18-bit High Speed Bi-CMOS Static RAM
For the availability of this product, please contact the sales office.
Description
CXK5B18120TM is a high speed 1M bit Bi-
44 pin TSOP (Plastic)
CMOS static RAM organized as 65536 words by
18 bits. Operating on a single 3.3V supply this
asynchronous IC is suitable for use in high speed
and low power applications.
Features
Single 3.3V Supply 3.3V±0.3V
Fast access time
12ns (Max.)
Low stand-by current: 10mA (Max.)
Low power operation 1116mW (Max.)
Package line-up
Dual Vcc/Vss
CXK5B18120TM 400mil 44pin TSOP Package
Function
65536-word × 18-bit static RAM
Structure
Silicon gate Bi-CMOS IC
Block Diagram
A14
A15
A9
A8
A12
A13
A11
A10
A5
A4
A3
A0
A2
A1
A6
A7
UB
LB
WE
OE
Buffer
Buffer
Row
Decoder
Pin configuration Pin Description
(Top View)
Symbol
Description
A4 1
A3 2
Memory Vcc
Matrix
256 × 4608
A2 3
A1 4
A0 5
CE 6
GND I/O1 7
I/O2 8
I/O3 9
I/O4 1
Vcc
0
11
I/O Gate
Column
Decoder
GND 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
I/O9 17
WE 18
I/O
Buffer
A15 19
A14 20
A13 21
A12 22
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 I/O18
37 I/O17
36 I/O16
35 I/O15
34 GND
33 Vcc
32 I/O14
31 I/O13
30 I/O12
29 I/O11
28 I/O10
27 NC
26 A8
25 A9
24 A10
23 A11
A0 to A15 Address input
I/O1 Data input output
to I/O9 (lower byte I/O)
I/O10
Data input output
to I/O18 (upper byte I/O)
CE Chip enable input
WE Write enable input
OE Output enable input
LB Lower byte select input
UB Upper byte select input
Vcc +3.3V Power supply
GND
Ground
NC No connection
CE
I/O1 I/O18
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93585A57-PK

1 page




CXK5B18120TM- pdf
Timing Waveform
Read cycle (1) : CE = OE = VIL, WE = VIH
Address
Data out
Previous data valid
tAA
tOH
tRC
Data valid
CXK5B18120TM
Read cycle (2) : WE = VIH
Address
CE
tAA
tCO
tLZ
OE
LB, UB
Data out
High impedance
tO
tOELZ
tLB
tU
B
tLBL
tUZBL
Z
tRC
tHZ
tOHZ
Data
valid
tLBH
tUZBH
Z
–5–

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