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PDF CXD2400R Data sheet ( Hoja de datos )
| Número de pieza | CXD2400R | |
| Descripción | Timing Controller for CCD cameras | |
| Fabricantes | Sony Corporation | |
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CXD2400R
Timing Controller for CCD cameras
Description
The CXD2400R is a timing controller for CCD
camera systems which use the ICX044/045,
ICX054/055 or other black/white CCD image
sensors.
48 pin LQFP (Plastic)
Features
• Supports EIA/CCIR standards
• Electronic iris (electronic shutter) function
• Sync signal generation function
• Supports external synchronization
• Supports non-interlacing
• Supports field/frame∗ accumulation
• Oscillator frequency: 1212 fh
(EIA: 19.0699MHz; CCIR: 18.9375MHz)
∗ The characteristics of CCD image sensors are
guaranteed for field accumulation operation.
Applications
CCD cameras
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD Vss – 0.5 to +7.5 V
• Input voltage
VI Vss – 0.5 to VDD + 0.5 V
• Output voltage
Vo Vss – 0.5 to VDD + 0.5 V
• Operating temperature Topr
–20 to +75 °C
• Storage temperature Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage
5.0V ± 0.25
• Operating temperature
–20 to +75
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93308D75-PS
1 page  
CXD2400R
Electrical Characteristics
1) DC Characteristics
(VDD = 5V ± 0.25V, Topr = –20 to +75°C)
Item
Symbol
Conditions
Min. Typ. Max. Unit
Supply voltage
VDD
4.75 5.0 5.25 V
Input voltage 1
VIH1
(All input pins except those below) VIL1
0.7VDD
0.3VDD
V
V
Input voltage 2
(Pins 22, 23 only in electronic
iris mode)
VIN2
2.0
VDD
V
Input voltage 3
(Pin 17 only in electronic
iris mode)
VIN3
VSS
VDD
V
Output voltage 1
VOH1
(All output pins except those below) VOL1
IOH = –2mA
IOL = 4mA
VDD – 0.8
V
0.4 V
Output voltage 2
(Pins 25, 26)
VOH2
VOL2
IOH = –4mA
IOL = 8mA
VDD – 0.8
V
0.4 V
Output voltage 3
(Pin 5)
VOH3
VOL3
IOH = –8mA
IOL = 8mA
VDD – 0.8
V
0.4 V
Output voltage 4
(Pins 2, 3)
VOH4
VOL4
ICH = –20mA
ICL = 20mA
VDD – 0.8
V
0.4 V
Output voltage 5
(Pin 47)
VOH5
VOL5
IOH = –3mA
IOL = 3mA
VDD/2
VDD/2
V
V
Output voltage 6
(Pin 45)
VOH6
VOL6
IOH = –4mA
IOL = 4mA
VDD – 0.8
V
0.4 V
Feedback resistance
RFB VIN = Vss or VDD
250k
1M
2.5M
Ω
Pull-up resistance
RPU
VIL = 0V
25k 50k 75k Ω
Pull-down resistance
RPD
VIH = VDD
25k 50k 75k Ω
Current consumption
VDD = 5V
IDD ICX054AL in normal
operating state
36
mA
∗ Power consumption: 180mW typ., ICX054AL load (in normal operating state)
2) Input/output capacitance
Item Symbol
Input pin capacitance
CIN
Output pin capacitance
COUT
Input/output pin capacitance CI/O
Min.
(VDD = V1 = 0V, fM = 1MHz)
Typ. Max. Unit
9 pF
11 pF
11 pF
–5–
5 Page 
CXD2400R
External Synchronization
1) External/internal sync selection
External or internal synchronization is selected automatically by a combination of 3 pins (VR/SYNC, HPLL and
ESYNC) to which the sync signal is input externally. The table below shows the input pattern combinations.
Input pattern
VR/SYNC pin: SYNC signal VR/SYNC pin: VD signal
VR/SYNC pin: Open
HPLL pin: Open
HPLL pin: HD signal
HPLL pin: Open
ESYNC pin: Open
ESYNC pin: VDD (power supply) ESYNC pin: Open
EXT pin output
High
High
Low
Sync state
External sync
External sync
Internal sync
Note) Operation is possible even if the VD cycle of the VD input in the VD/HD sync mode is longer than normal.
The EXT pin is the external/internal sync identification signal output pin. This output signal can be used as the
signal to select LC oscillation for expanding the lock range for external synchronization or the oscillator for
improving the oscillation accuracy for internal synchronization.
2) Modes for external synchronization
Field accumulation
Frame accumulation∗
Interlace
O
O
SYNC
synchronization Non-interlace
×
(Cannot be accomplished
since interlace operation
is the prior condition.)
×
(Cannot be accomplished
since interlace operation
is the prior condition.)
Interlace
O
O
VD/HD
synchronization Non-interlace
×
O (Not practically applicable since
the sensitivity is halved.)
∗ The characteristics of CCD image sensors are guaranteed for field accumulation operation.
3) Reset operation
SYNC synchronization
The VR1 signal component is extracted from the SYNC signal supplied externally and, for EIA, V reset is
performed so that the VDO pulse falls at the count of 259H (262.5 – 3.5H) from the fall of the VR1 pulse. For
CCIR, it is reset in such a way that the VDO pulse falls at the count of 309H (312.5 – 3.5H). For these reasons,
it is a prerequisite that the SYNC signal input comply with the EIA or CCIR standard.
VD/HD synchronization
V reset is performed so that the VDO pulse falls 1H later after detecting the fall of the VD (VDR) pulse supplied
externally. Therefore, this enables V reset operation regardless of the field line number. The phase difference
between the VDR pulse and HDO pulse which is locked horizontally at PLL circuit identifies whether the field is
odd or even. (VDR must have a pulse width of 2H or more.)
– 11 –
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CXD2400R.PDF ] | |
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