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PDF CXD1179Q Data sheet ( Hoja de datos )
| Número de pieza | CXD1179Q | |
| Descripción | 8-bit 35MSPS Video A/D Converter with Clamp Function | |
| Fabricantes | Sony Corporation | |
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CXD1179Q
8-bit 35MSPS Video A/D Converter with Clamp Function
Description
The CXD1179Q is an 8-bit CMOS A/D converter
for video with synchronizing clamp function. The
adoption of 2 step-parallel method achieves ultra-low
power consumption and a maximum conversion
speed of 35MSPS.
32 pin QFP (Plastic)
Features
• Resolution: 8-bit ± 1/2LSB (DL)
• Maximum sampling frequency: 35MSPS
• Low power consumption: 80 mW (at 35MSPS typ.)
(reference current excluded)
• Synchronizing clamp function
• Clamp ON/OFF function
• Reference voltage self bias circuit
• Input CMOS compatible
• 3-state TTL compatible output
• Single 5V power supply
• Low input capacitance: 8 pF
• Reference impedance: 330 Ω (typ.)
Applications
Wide range of applications that require high-speed
A/D conversion such as TV and VCR.
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage VDD
7V
• Reference voltage
VRT, VRB VDD + 0.5 to VSS – 0.5 V
• Input voltage VIN
VDD + 0.5 to VSS – 0.5 V
(Analog)
• Input voltage VI
VDD + 0.5 to VSS – 0.5 V
(Digital)
• Output voltage VO
VDD + 0.5 to VSS – 0.5 V
(Digital)
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage AVDD, AVSS 4.75 to 5.25
V
DVDD, DVSS
| DVSS – AVSS | 0 to 100
mV
• Reference input voltage
VRB 0 and above V
VRT 2.7 and below V
• Analog input VIN
1.8 Vp-p above
• Clock pulse width
Tpw1, Tpw0 13 ns (min) to 1.1 µs (max)
• Operating ambient temperature
Topr
–40 to +85 °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E91Z07G86-TE
1 page  
Pin No. Symbol
26 VREF
Equivalent circuit
AVDD
26
AVSS
CXD1179Q
Description
Clamp reference voltage input.
Clamps so that the reference voltage
and the input signal during clamp
interval are equal.
27 CCP
28, 31 DVSS
29 CLE
AVDD
27
AVSS
DVDD
29
DVSS
Integrates the clamp control voltage.
The relationship between the changes
in CCP voltage and in VIN voltage is
positive phase.
Digital ground
CLAMP
PULSE
The clamp function is enabled when
CLE = Low.
The clamp function is set to off and
the converter functions as a normal
A/D converter when CLE = High.
The clamp pulse can be measured by
connecting CLE to DVDD through a
several hundred Ω resistor.
30 OE
32 NC
DVDD
30
DVSS
—5—
Data is output when OE = Low.
Pins D0 to D7 are at high impedance
when OE = High.
NC pin
5 Page 
CXD1179Q
2. This IC uses an offset cancel type comparator and the comparator operates synchronously with an
external clock. These modes are respectively indicated on the timing chart with S, H, C symbols. That is,
the comparator performs input sampling (auto zero) mode, input hold mode and comparison mode using
the external clock.
3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled
with the falling edge of the first clock by means of the upper comparator block and the lower comparator A
block.
The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock.
Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to
the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the
second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock.
Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.
Operation Notes
1. Power supply and ground
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital
and analog power supply pins, use a ceramic capacitor of about 0.1 µF set as close as possible to the pin
to bypass to the respective grounds.
2. Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.
However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.
When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be
prevented by inserting a resistance of about 100 Ω in series between the amplifier output and A/D input.
3. Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals,
separate it from other circuits.
4. Reference input
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
VRB pins to analog ground, by means of a capacitor about 0.1 µF, the stable characteristics of the
reference voltage are obtained. By shorting VRT and VRTS, VRB and VRBS, the self-bias function that
generates VRT = about 2.6 V and VRB = about 0.6 V, is activated.
5. Timing
Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks
and with the following rising edge. The delay from the clock rising edge to the data output is about 13ns.
6. OE pin
By connecting OE to DVSS output mode is obtained. By connecting OE to DVDD high impedance is
obtained.
—11—
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CXD1179Q.PDF ] | |
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