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PDF CXB1562AQ Data sheet ( Hoja de datos )

Número de pieza CXB1562AQ
Descripción 2R IC for Optical Fiber Communication Receiver
Fabricantes Sony Corporation 
Logotipo Sony Corporation Logotipo



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CXB1562AQ
2R IC for Optical Fiber Communication Receiver
Description
The CXB1562AQ achieves the 2R optical-fiber
communication receiver functions (Reshaping and
Regenerating) on a single chip. This IC is also
equipped with the signal interruption alarm output
function, which is used to discriminate the existence
of data input.
32 pin QFP (Plastic)
Features
Auto-offset canceler circuit
Signal interruption alarm output
2-level switching function of identification maximum voltage amplitude for alarm block
Single 5V power supply
Applications
FDDI
: 125Mb/s
SONET/SDH : 155.52Mb/s
ESCON
: 200Mb/s
Fiber channel : 265.625Mb/s
Absolute Maximum Ratings
Supply voltage
Storage temperature
Input voltage difference : I VD – VD I
SW input voltage
Output current (Continuous)
(Surge current)
VCC – VEE
Tstg
Vdif
Vi
IO
–0.3 to +7.0
–65 to +150
0.0 to +2.5
VEE to VCC
0 to 50
0 to 100
V
°C
V
V
mA
mA
Recommended Operating Conditions
Supply voltage
VCC – VEE
Termination voltage (for data/alarm) VCC – VT1
Termination voltage (for alarm 2)
VT2
Termination resistance (for data/alarm) RT1
Termination resistance (for alarm 2) RT2
Operating temperature
Ta
5.0±0.5
1.8 to 2.2
VEE
45 to 55
460 to 560
–40 to +85
V
V
V
°C
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94930B6Z

1 page




CXB1562AQ pdf
CXB1562AQ
Typical pin
Pin No. Symbol voltage (V)
DC AC
28 CAP3 –1.8V
29 CAP2 –1.8V
Equivalent circuit
Description
29
80
5µA
28
VCCA Connects a peak hold circuit
capacitor for alarm block. 470pF
80 should be connected to VccA
each.
CAP2 pin Peak hold
capacitor connection for
alarm level setting block.
CAP3 pin Peak hold
5µA capacitor connection for
limiting amplifier signal.
VEEA
–0.84V
30
DOWN
(for
VEEI
= –5V)
–0.8V
31 UP
(for
VEEI
= –5V)
32 VccA 0V
31
30
3
993
110.3
110.3
Vcs
VccA
SW
VEEA
Connects a resistor for alarm
level setting.
Default voltage can be
generated without an external
resistor by shorting the VEEI pin
to VEEA.
Positive power supply for analog
block.
–5–

5 Page





CXB1562AQ arduino
CXB1562AQ
Notes on Operation
1. Limiting amplifier block
The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and
C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and
IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external
capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since
peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on
the f1/f2 combination, set the C1 and C2 so as to avoid the occurrence of peaking characteristics. The target
values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is
used, provide AC grounding by connecting Pin 6 to a capacitor which has the same capacitance as capacitor
C1.
R1 (internal): 1.5k
R2 (internal): 10k
f2: 4.8kHz
f1: 72Hz
C1 (external): 0.022µF
C2 (external): 0.22µF
1kis incorporated between Pins 8 and 9; 2kbetween Pins 10 and 11. A resistance value which is to be
inserted in parallel with a capacitor f2 can be selected 5 ways (, 3k, 2k, 1k, 1k//2k) by external wiring,
and DC feedback can be varied.
D5
C1
6
C1
8
9
C2
10
11
R1
R3
R4
R1
R2
R2
Fig. 1
To IC interior
Feedback
frequency response
Amplifier
frequency response
f1 f2
Frequency
Fig. 2
– 11 –

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