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PDF CY7C143 Data sheet ( Hoja de datos )
| Número de pieza | CY7C143 | |
| Descripción | 2K x 16 Dual-Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C133
CY7C143
2K x 16 Dual-Port Static RAM
Features
• True dual-ported memory cells which allow
simultaneous reads of the same memory location
• 2K x 16 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 25/35/55 ns
• Low operating power: ICC = 150 mA (typ.)
• Fully asynchronous operation
• Master CY7C133 expands data bus width to 32 bits or
more using slave CY7C143
• BUSY output flag on CY7C133; BUSY input flag on
CY7C143
• Available in 68-pin PLCC
Logic Block Diagram
CEL
R/WLUB
Functional Description
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16
dual-port static RAMs. Two ports are provided permitting
independent access to any location in memory. The CY7C133
can be utilized as either a stand-alone 16-bit dual-port static
RAM or as a master dual-port RAM in conjunction with the
CY7C143 slave dual-port device in systems requiring 32-bit or
greater word widths. It is the solution to applications requiring
shared or buffered data, such as cache memory for DSP,
bit-slice, or multiprocessor designs.
Each port has independent control pins; Chip Enable (CE),
Write Enable (R/WUB, R/WLB), and Output Enable (OE).
BUSY signals that the port is trying to access the same
location currently being accessed by the other port. An
automatic power-down feature is controlled independently on
each port by the Chip Enable (CE) pin.
The CY7C133 and CY7C143 are available in 68-pin PLCC.
CER
R/WRUB
R/WLLB
OEL
R/WRLB
OER
I/O8L – I/O15L
I/O0L – I/O7L
BUSYL[1]
A10L
A0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
CE L
OE L
R/WLUB
R/WLLB
ARBITRATION
LOGIC
(CY7C133 ONLY)
CER
OER
R/WRUB
R/WRLB
Note:
1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.
I/O8R – I/O15R
I/O0R – I/O7R
1[ ]
BUSYR
A10R
A0R
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06036 Rev. *B
Revised June 22, 2004
1 page  
CY7C133
CY7C143
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State .....................................................−0.5V to +7.0V
DC Input Voltage ................................................. −3.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
−40°C to +85°C
VCC
5V ± 10%
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VOH Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL Output LOW Voltage
IOL = 4.0 mA
IOL = 16.0 mA[5]
VIH Input HIGH Voltage
VIL Input LOW Voltage
IIX Input Leakage Current
GND < VI < VCC
IOZ Output Leakage Current GND < VO < VCC, Output Disabled
IOS Output Short Circuit Current[6,7] VCC = Max., VOUT = GND
ICC
VCC Operating Supply Current
CE = VIL,
Outputs Open,
f
=
fMAX[8]
Com’l
Ind.
ISB1
Standby Current Both Ports, TTL CEL and CER > VIH, f = fMAX[8]
Com’l
Inputs
Ind.
ISB2
Standby Current One Port, TTL
Inputs
COEutLpourtsCOEpRe>n,VfIH=,fAMcAtXiv[8e] Port
Com’l
Ind.
ISB3
Standby Current Both Ports,
Both Ports CEL and CER > VCC – Com’l
CMOS Inputs
0.2V, VIN > VCC – 0.2V or VIN < Ind.
0.2V, f = 0
ISB4
Standby Current One Port,
One Port CEL or CER > VCC – 0.2V, Com’l
CMOS Inputs
VIN > VCC – 0.2V or
Vf =INfM<A0X.[82]V, Active Port Outputs Open,
Ind.
7C133-25
7C143-25
Min. Typ. Max.
2.4
0.4
0.5
2.2
0.8
−5 +5
−5 +5
−200
170 250
170 290
40 60
40 75
100 140
100 160
3 15
3 15
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
90 120 mA
90 140
Electrical Characteristics Over the Operating Range (continued)
7C133-35
7C143-35
7C133-55
7C143-55
Parameter
Description
Test Conditions
Min. Typ. Max. Min. Typ. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA
2.4
2.4
V
VOL Output LOW Voltage IOL = 4.0 mA
IOL = 16.0 mA[5]
0.4 0.4 V
0.5 0.5
VIH Input HIGH Voltage
2.2 2.2
V
VIL Input LOW Voltage
0.8 0.8 V
IIX Input Leakage Current GND < VI < VCC
−5 +5 −5
+5 µA
Notes:
5. BUSY pin only.
6. Duration of the short circuit should not exceed 30 seconds.
7. Tested initially and after any design or process changes that may affect these parameters.
8. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V.
Document #: 38-06036 Rev. *B
Page 5 of 13
5 Page 
Switching Waveforms (continued)
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
tRC or tWC
ADDRESSL
ADDRESS MATCH
tPS
ADDRESSR
BUSYR
tBLA
Right Address Valid First:
ADDRESSR
tRC or tWC
ADDRESS MATCH
tPS
ADDRESSL
BUSY L
tBLA
Busy Timing Diagram No. 3
Write with BUSY (For Slave CY7C143)
CE
R/W
BUSY
tWB
ADDRESS MISMATCH
tBHA
ADDRESS MISMATCH
tBHA
tPWE
tWH
CY7C133
CY7C143
Document #: 38-06036 Rev. *B
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CY7C143.PDF ] | |
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