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PDF CY7C106B Data sheet ( Hoja de datos )
| Número de pieza | CY7C106B | |
| Descripción | 256K x 4 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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1CY7C1006B
CY7C106B
CY7C1006B
Features
• High speed
— tAA = 12 ns
• CMOS for optimum speed/power
• Low active power
— 495 mW
• Low standby power
— 275 mW
• 2.0V data retention (optional)
— 100 µW
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Functional Description
The CY7C106B and CY7C1006B are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
256K x 4 Static RAM
Enable (CE), an active LOW Output Enable (OE), and
three-state drivers. These devices have an automatic pow-
er-down feature that reduces power consumption by more
than 65% when the devices are deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O0 through I/O3) is then written into the location speci-
fied on the address pins (A0 through A17).
Reading from the devices is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the four I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE and WE LOW).
The CY7C106B is available in a standard 400-mil-wide SOJ;
the CY7C1006B is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
INPUT BUFFER
A1
A2
A3
A4
A5 512 x 512 x 4
A6 ARRAY
A7
A8
A9
Pin Configuration
I/O3
I/O2
I/O1
I/O0
SOJ
Top View
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
OE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 A17
26 A16
25
24
23
22
A15
A14
A13
A12
21 A11
20 NC
19 I/O3
18
17
16
I/O2
I/O1
I/O0
15 WE
C106B–2
COLUMN
DECODER
POWER
DOWN
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum Standby
Current (mA)
7C106B-12
7C1006B-12
12
90
50
CE
WE
OE
C106B–1
7C106B-15
7C1006B-15
15
80
30
7C106B-20
7C1006B-20
20
75
30
7C106B-25
7C1006B-25
25
70
30
7C106B-35
35
60
25
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05037 Rev. **
Revised August 24, 2001
1 page  
CY7C106B
CY7C1006B
Switching Characteristics Over the Operating Range[5]
7C106B-12 7C106B-15 7C106B-20 7C106B-25
7C1006B-12 7C1006B-15 7C1006B-20 7C1006B-25 7C106B-35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time
12 15 20 25 35 ns
tAA Address to Data Valid
12 15 20 25 35 ns
tOHA
Data Hold from Address Change 3
3
3
3
3 ns
tACE CE LOW to Data Valid
12 15 20 25 35 ns
tDOE
OE LOW to Data Valid
6 7 8 10 10 ns
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
0 0 0 0 0 ns
6 7 8 10 10 ns
3 3 3 3 3 ns
6 7 8 10 10 ns
tPU CE LOW to Power-Up
0 0 0 0 0 ns
tPD CE HIGH to Power-Down
WRITE CYCLE[8, 9]
12 15 20 25 35 ns
tWC Write Cycle Time
12 15 20 25 35 ns
tSCE CE LOW to Write End
10 12 15 20 25 ns
tAW
Address Set-Up to Write End
10
12
15
20
25 ns
tHA
Address Hold from Write End
0
0
0
0
0 ns
tSA
Address Set-Up to Write Start
0
0
0
0
0 ns
tPWE
WE Pulse Width
10 12 15 20 25 ns
tSD Data Set-Up to Write End
7
8 10 15 20 ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low Z[7]
WE LOW to High Z[6, 7]
0 0 0 0 0 ns
2 3 3 3 3 ns
6 7 8 10 10 ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30–pF load capacitance.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05037 Rev. **
Page 5 of 10
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| PDF Descargar | [ Datasheet CY7C106B.PDF ] | |
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