|
|
PDF CY7C1061AV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1061AV33 | |
| Descripción | 16-Mbit (1 M × 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C1061AV33 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
CY7C1061AV33
16-Mbit (1 M × 16) Static RAM
16-Mbit (1 M × 16) Static RAM
Features
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ 990 mW (max)
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE1 and CE2 features
■ Available in Pb-free and non Pb-free 54-pin TSOP II package
and non Pb-free 60-ball fine-pitch ball grid array (FBGA)
package
Functional Description
The CY7C1061AV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, enable the chip (CE1 LOW and CE2 HIGH)
while forcing the Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7),
is written into the location specified on the address pins (A0
through A19). If Byte High Enable (BHE) is LOW, then data from
I/O pins (I/O8 through I/O15) is written into the location specified
on the address pins (A0 through A19).
To read from the device, enable the chip by taking CE1 LOW and
CE2 HIGH while forcing the Output Enable (OE) LOW and the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins will
appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then
data from memory will appear on I/O8 to I/O15. See Truth Table
on page 11 for a complete description of Read and Write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE1
HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE
and BLE are disabled (BHE, BLE HIGH), or a Write operation is
in progress (CE1 LOW, CE2 HIGH, and WE LOW).
For a complete list of related documentation, click here.
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
AA34
A5
1M x 16
ARRAY
A6
AAA789
I/O0–I/O7
I/O8–I/O15
COLUMN
DECODER
BHE
WE
OE
BLE
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05256 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 16, 2015
1 page  
CY7C1061AV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on
VCC to Relative GND [5] ...............................–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State [5] ................................ –0.5 V to VCC + 0.5 V
DC Input Voltage [5] ............................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0 C to +70 C
–40 C to +85 C
VCC
3.3 V 0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH Output HIGH Voltage
IOH = –4.0 mA
VOL Output LOW Voltage
IOL = 8.0 mA
VIH Input HIGH Voltage
VIL Input LOW Voltage [5]
IIX
Input Leakage Current
GND < VI < VCC
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply Current VCC = max, f = fmax = 1/tRC
Commercial
Industrial
ISB1
Automatic CE Power-down
Current – TTL Inputs
CE2 < VIL, Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fmax
ISB2
Automatic CE Power-down
Current – CMOS Inputs
CE2 < 0.3 V, Max VCC,
Commercial
/ Industrial
CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V,
f=0
Min
2.4
–
2.0
–0.3
–1
–1
–
–
–
-10
Max
–
0.4
VCC + 0.3
0.8
+1
+1
275
275
70
Unit
V
V
V
V
A
A
mA
mA
mA
– 50 mA
Note
5. VIL(min) = –2.0 V for pulse durations of less than 20 ns.
Document Number: 38-05256 Rev. *M
Page 5 of 17
5 Page 
CY7C1061AV33
Truth Table
CE1 CE2 OE WE BLE
HX XX
X
X L XX X
L H LH L
L H LH L
L H LH H
L HXL
L
L HXL
L
LHXL H
L H HH X
BHE
I/O0–I/O7
X High Z
X High Z
L Data Out
H Data Out
L High Z
L Data In
H Data In
L High Z
X High Z
I/O8–I/O15
High Z
High Z
Data Out
High Z
Data Out
Data In
High Z
Data In
High Z
Mode
Power Down
Power Down
Read All Bits
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
Power
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Document Number: 38-05256 Rev. *M
Page 11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CY7C1061AV33.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C1061AV33 | 16-Mbit (1 M × 16) Static RAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |