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PDF CY7C346-30HC Data sheet ( Hoja de datos )
| Número de pieza | CY7C346-30HC | |
| Descripción | USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) | |
| Fabricantes | Cypress Semiconductor | |
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USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Features
• 128 macrocells in eight logic array blocks (LABs)
• 20 dedicated inputs, up to 64 bidirectional I/O pins
• Programmable interconnect array
• 0.8-micron double-metal CMOS EPROM technology
• Available in 84-pin CLCC, PLCC, and 100-pin PGA,
PQFP
Functional Description
The CY7C346 is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX® architecture is
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
128-Macrocell MAX® EPLD
The 128 macrocells in the CY7C346 are divided into eight
LABs, 16 per LAB. There are 256 expander product terms, 32
per LAB, to be used and shared by the macrocells within each
LAB.
Each LAB is interconnected through the programmable inter-
connect array, allowing all signals to be routed throughout the
chip.
The speed and density of the CY7C346 allow it to be used in
a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 25 times the functionality
of 20-pin PLDs, the CY7C346 allows the replacement of over
50 TTL devices. By replacing large amounts of logic, the
CY7C346 reduces board space, part count, and increases
system reliability.
Logic Block Diagram
.. 1 (C7) [16] . INPUT/CLK
. 78 (A10) [9] ..... INPUT
. 79 (B9) [10] ..... INPUT
80 (A9) [11] ..... INPUT
. 83 (A8) [14] ..... INPUT
. 84 (B7) [15] ..... INPUT
.. 2 (A7) [17] ..... INPUT
.. 5 (C6) [20] ..... INPUT
.. 6 (A5) [21] ..... INPUT
.. 7 (B5) [22] ..... INPUT
INPUT [59] (N4) . 36
INPUT [60] (M5) . 37
INPUT [61] (N5) . 38
INPUT [64] (N6) . 41
INPUT [65] (M7) . 42
INPUT [66] (L7) . 43
INPUT [67] (N7) . 44
INPUT [70] (L8) . 47
INPUT [71] (N9) . 48
INPUT [72] (M9) . 49
8 (B13) [1]
9 (C12) [2]
10 (A13) [3]
11 (B12) [4]
12 (A12) [5]
13 (11) [6]
NC (A11) [7]
NC (B10) [8]
LAB A
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELL 7
MACROCELL 8
MACROCELL 9–16
SYSTEM CLOCK
14 (A4) [23]
15 (B4) [24]
16 (A3) [25]
17 (A2) [26]
18 (B3) [27]
21 (A1) [28]
NC (B2) [29]
NC (B1) [30]
LAB B
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22
MACROCELL 23
MACROCELL 24
MACROCELL 25–32
22 (C2) [31]
25 (C1) [32]
26 (D2) [33]
27 (D1) [34]
28 (E2) [35]
29 (E1) [36]
NC (F1) [39]
NC (G2) [40]
LAB C
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
MACROCELL 38
MACROCELL 39
MACROCELL 40
MACROCELL 41–48
30 (G3) [41]
31 (G1) [42]
32 (H3) [45]
33 (J1) [46]
34 (J2) [47]
35 (K1) [48]
NC (K2) [49]
NC (L1) [50]
LAB D
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
MACROCELL 57– 64
3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8) [18, 19, 43, 44, 68, 69, 93, 94]
16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6) [12, 13, 37, 38, 62, 63, 87, 88]
P
I
A
VCC
GND
LAB H
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL 121–128
LAB G
MACROCELL 104
MACROCELL 103
MACROCELL 102
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
MACROCELL 105–112
[100] (C13) NC
[99] (D12) NC
[98] (D13) 77
[97] (E12) 76
[96] (E13) 75
[95] (F11) 74
[92] (G13) 73
[91] (G11) 72
[90] (G12) NC
[89] (H13) NC
[86] (J13) 71
[85] (J12) 70
[84] (K13) 69
[83] (K12) 68
[82] (L13) 67
[81] (L12) 64
LAB F
MACROCELL 88
MACROCELL 87
MACROCELL 86
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 86–96
[80] (M13) NC
[79] (M12) NC
[78] (N13) 63
[77] (M11) 60
[76] (N12) 59
[75] (N11) 58
[74] (M10) 57
[73] (N10) 56
LAB E
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MACROCELL 66
MACROCELL 65
MACROCELL 73– 80
[58] (M4) NC
[57] (N3) NC
[56] (M3) 55
[55] (N2) 54
[54] (M2) 53
[53] (N1) 52
[52] (L2) 51
[51] (M1) 50
() – PERTAIN TO 100-PIN PGA PACKAGE
[ ] –PERTAIN TO 100-PIN PQFP PACKAGE
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03005 Rev. *B
Revised April 19, 2004
1 page  
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the entire
device.
The CY7C346 is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
Typical ICC vs. fMAX
400
300
VCC = 5.0V
Room Temp.
200
100
0
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
MAXIMUM FREQUENCY
Output Drive Current
100
IOL
80
VCC = 5.0V
60 Room Temp.
40
IOH
20
0 0.45 1 2 3 4
VO OUTPUT VOLTAGE (V)
5
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay tEXP to the overall delay. Similarly, there is an
additional tPIA delay for an input from an I/O pin when
compared to a signal from straight input pin.
When calculating synchronous frequencies, use tS1 if all
inputs are on dedicated input pins. The parameter tS2 should
be used if data is applied at an I/O pin. If tS2 is greater than
tCO1, 1/tS2 becomes the limiting frequency in the data path
mode unless 1/(tWH + tWL) is less than 1/tS2.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tS1. Determine which
of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest
frequency. The lowest of these frequencies is the maximum
data path frequency for the synchronous configuration.
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on the dedicated input pins. If any data
is applied to an I/O pin, tAS2 must be used as the required
set-up time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH)
becomes the limiting frequency in the data path mode unless
1/(tAWH + tAWL) is less than 1/(tAS2 + tAH).
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tAS1. Determine
which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous config-
uration.
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same
synchronous clock. If tOH is greater than the minimum
required input hold time of the subsequent synchronous
logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case
environmental and supply voltage conditions.
The parameter tAOH indicates the system compatibility of this
device when driving subsequent registered logic with a
positive hold time and using the same asynchronous clock
as the CY7C346.
In general, if tAOH is greater than the minimum required input
hold time of the subsequent logic (synchronous or
asynchronous) then the devices are guaranteed to function
properly under worst-case environmental and supply voltage
conditions, provided the clock signal source is the same.
This also applies if expander logic is used in the clock signal
path of the driving device, but not for the driven device. This
is due to the expander logic in the second device’s clock
signal path adding an additional delay (tEXP) causing the
output data from the preceding device to change prior to the
arrival of the clock signal at the following device’s register.
Document #: 38-03005 Rev. *B
Page 5 of 21
5 Page 
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C346
Military External Asynchronous Switching Characteristics[6] Over Operating Range
Parameter
tACO1
tACO2
tAS1
tAS2
tAH
tAWH
tAWL
tACF
tAP
fMAXA1
fMAXA2
fMAXA3
fMAXA4
tAOH
Description
Asynchronous Clock Input to Output Delay[7]
Asynchronous Clock Input to Local Feedback to
Combinatorial Output[20]
Dedicated Input or Feedback Set-Up Time to
Asynchronous Clock Input[7]
I/O Input Set-Up Time to Asynchronous Clock
Input[7]
Input Hold Time from Asynchronous Clock Input[7]
Asynchronous Clock Input HIGH Time[7]
Asynchronous Clock Input LOW Time[7, 21]
Asynchronous Clock to Local Feedback Input[4, 22]
External Asynchronous Clock Period (1/(fMAXA4))[4]
External Feedback Maximum Frequency in
Asynchronous Mode (1/(tACO1 + tAS1))[4, 23]
Maximum Internal Asynchronous Frequency[4, 24]
Data Path Maximum Frequency in Asynchronous
Mode[4, 25 ]
Maximum Asynchronous Register Toggle
Frequency 1/(tAWH + tAWL)[4, 26]
Output Data Stable Time from Asynchronous Clock
Input[4, 27]
7C346-30
Min.
Max.
30
46
6
22
8
14
11
18
25
27.7
40
33.3
40
15
7C346-35
Min. Max.
35
55
8
28
10
16
14
22
30
23.2
33.3
28.5
33.3
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
ns
Document #: 38-03005 Rev. *B
Page 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet CY7C346-30HC.PDF ] | |
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