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DE28F800B3B150 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer DE28F800B3B150
Beschreibung FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
DE28F800B3B150 Datasheet, Funktion
E
PRODUCT PREVIEW
FAST BOOT BLOCK
FLASH MEMORY FAMILY
8 AND 16 MBIT
28F800F3, 28F160F3
Includes Extended and Automotive Temperature Specifications
n High Performance
54 MHz Effective Zero Wait-State
Performance
Synchronous Burst-Mode Reads
Asynchronous Page-Mode Reads
n SmartVoltage Technology
2.7 V3.6 V Read and Write
Operations for Low Power Designs
12 V VPP Fast Factory Programming
n Flexible I/O Voltage
1.65 V I/O Reduces Overall System
Power Consumption
5 V-Safe I/O Enables Interfacing to
5 V Devices
n Enhanced Data Protection
Absolute Write Protection with
VPP = GND
Block Locking
Block Erase/Program Lockout
during Power Transitions
n Density Upgrade Path
8- and 16-Mbit
n Manufactured on ETOX™ V Flash
Technology
n Supports Code Plus Data Storage
Optimized for Flash Data Integrator
(FDI) Software
Fast Program Suspend Capability
Fast Erase Suspend Capability
n Flexible Blocking Architecture
Eight 4-Kword Blocks for Data
32-Kword Main Blocks for Code
Top or Bottom Configurations
Available
n Extended Cycling Capability
Minimum 10,000 Block Erase Cycles
Guaranteed
n Low Power Consumption
Automatic Power Savings Mode
Decreases Power Consumption
n Automated Program and Block Erase
Algorithms
Command User Interface for
Automation
Status Register for System
Feedback
n Industry-Standard Packaging
56-Lead SSOP
µBGA* CSP
Intel’s Fast Boot Block memory family renders high performance asynchronous page-mode and synchronous
burst reads making it an ideal memory solution for burst CPUs. Combining high read performance with the
intrinsic non-volatility of flash memory, this flash memory family eliminates the traditional redundant memory
paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory for
improved system performance. Therefore, it reduces the total memory requirement which helps increase
reliability and reduce overall system power consumption and cost.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They are available
in industry-standard packages: the µBGA* CSP, ideal for board-constrained applications, and the rugged
56-lead SSOP.
May 1998
Order Number: 290644-001






DE28F800B3B150 Datasheet, Funktion
FAST BOOT BLOCK DATASHEET
E
2.0 PRODUCT DESCRIPTION
This section describes the pinout and block
architecture of the device family.
to the 16-Mbit density. The family is available in
µBGA CSP and 56-lead SSOP packages. Pinouts
for the 8- and 16-Mbit components are illustrated in
Figures 1 and 2.
2.1 Pinouts
Intel’s Fast Boot Block flash memory family
provides upgrade paths in each package pinout up
2.2 Pin Description
The pin description table describes pin usage.
1 2 3 4 5 6 7 8 9 10
A
A15 A12
GND CLK VCC VPP
A4 A1
B 32M 16M
A14
A11
A8
A20 ADV# WE# A19
A17
A5
A2
C 64M
A13 A10 A9 A21 RST# WP# A18 A7 A6 A3
D
VCCQ DQ7 DQ13 DQ12 DQ4 DQ11 DQ10 DQ9 DQ0 CE#
E
A16 DQ15 DQ6 DQ5 VCC DQ3 DQ2 DQ1 OE#
A0
F
WAIT# GND DQ14 GND
VCCQ DQ8 GND
NOTES:
1. Shaded connections indicate upgrade address connections. Lower density devices will not have upper address solder
balls. Routing is not recommended in this area.
2. A20 and A21 are the upgrade address for potential 32-Mbit and 64-Mbit devices (currently not on road map).
3. Reference the Micro Ball Grid Array Package Mechanical Specification and Media Information on Intel’s World Wide Web
home page for detailed package specifications.
Figure 1. 56-Ball µBGA* Package Pinout (Top View, Ball Down)
6 PRODUCT PREVIEW

6 Page









DE28F800B3B150 pdf, datenblatt
FAST BOOT BLOCK DATASHEET
E
3.0 PRINCIPLES OF OPERATION
The Fast Boot Block flash memory components
include an on-chip WSM to manage block erase
and program. It allows for CMOS-level control
inputs, fixed power supplies, and minimal processor
overhead with RAM-like interface timings.
3.1 Bus Operations
All bus cycles to and from flash memory conform to
standard microprocessor bus cycles.
3.1.1
READ
The flash memory has three read modes available:
read array, identifier codes, and status register.
These modes are accessible independent of the
VPP voltage. The appropriate read command (Read
Array, Read Identifier Codes, or Read Status
Register) must be written to the CUI to enter the
requested read mode. Upon initial power-up or exit
from reset, the device defaults to read array mode.
When reading information from main blocks in read
array mode, the device supports two high-
performance read configurations: asynchronous
page-mode and synchronous burst-mode.
Asynchronous page-mode is the default state and
provides high data transfer rate for non-clocked
memory subsystems. In this state, data is internally
read and stored in a high-speed page buffer. A1:0
addresses data in the page buffer. The page size is
four words. The other read configuration,
synchronous burst-mode, is enabled by writing to
read configuration register. This register sets the
read configuration, burst order, frequency
configuration, and burst length. In synchronous
burst-mode, the device latches the initial address
then outputs a sequence of data with respect to the
input CLK and read configuration setting.
Read operations from the parameter blocks,
identifier codes and status register transpire as
single asynchronous or synchronous read cycles.
The read configuration register setting determines
whether or not read operations are asynchronous or
synchronous.
For all read operations, CE# must be driven active
to enable the devices, ADV# must be driven low to
open the internal address latch, and OE# must be
driven low to activate the outputs. In asynchronous
mode, the address is latched when ADV# is driven
high. In synchronous mode, the address is latched
by ADV# going high or ADV# low in conjunction
with a rising (falling) clock edge, whichever occurs
first. WE# must be at VIH. Figures 14 through 19
illustrate different read cycles.
3.1.2
OUTPUT DISABLE
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0–DQ15 are
placed in a high-impedance state.
3.1.3
STANDBY
Deselecting the device by bringing CE# to a logic-
high level (VIH) places the device in standby mode,
which substantially reduces device power
consumption. In standby, outputs are placed in a
high-impedance state independent of OE#. If
deselected during program or erase operation, the
device continues to consume active power until the
program or erase operation is complete.
3.1.4
WRITE
Commands are written to the CUI using standard
microprocessor write timings when ADV#, WE#,
and CE# are active and OE# inactive. The CUI
does not occupy an addressable memory location.
The address is latched on the rising edge of ADV#,
WE#, or CE# (whichever occurs first) and data
needed to execute a command is latched on the
rising edge of WE# or CE# (whichever goes high
first). Write operations are asynchronous.
Therefore, CLK is ignored during write operations.
Figure 20 illustrates a write operation.
12 PRODUCT PREVIEW

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