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PDF LU3X34FTR-HS128-DB Data sheet ( Hoja de datos )
| Número de pieza | LU3X34FTR-HS128-DB | |
| Descripción | Quad 3 V 10/100 Ethernet Transceiver TX/FX | |
| Fabricantes | Agere Systems | |
| Logotipo |  |
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Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Overview
The LU3X34FTR is a fully integrated, 4-port
10/100 Mbits/s physical layer device with an inte-
grated transceiver. This part was designed specifi-
cally for 10/100 Mbits/s switches. These applications
typically require stringent functionality in addition to
very tight board space, power, and cost require-
ments. The LU3X34FTR supports RMII and SMII
interfaces, offering the designer multiple reduced pin
count interfaces to save both real estate and cost in
system design. The LU3X34FTR was designed from
the beginning to conform fully with all pertinent spec-
ifications, from the ISO1/IEC2 11801 and EIA3/TIA
568 cabling guidelines to ANSI4 X3.263TP-PMD to
IEEE 5 802.3 Ethernet specifications.
Features
s 4-port, single-chip, integrated physical layer and
transceivers for 10Base-T, 100Base-TX, or
100Base-FX functions.
s IEEE 802.3 compatible 10Base-T and 100Base-T
physical layer interface and ANSI X3.263 TP-PMD
compatible transceiver.
s Interface support for RMII and SMII switch
applications.
s Autonegotiation pin configurability on a per-port
basis.
s FX mode configurable on a per-port basis.
s Built-in analog 10 Mbit receive filter, removing the
need for external filters.
s Built-in 10 bit transmit filter.
s 10 Mbit PLL, exceeding tolerances for both
preamble and data jitter.
s 100 Mbit PLL, combined with the digital adaptive
equalizer, robustly handles variations in rise-fall
time, excessive attenuation due to channel loss,
duty-cycle distortion, crosstalk, and baseline
wander.
s Transmit rise-fall time manipulated to provide lower
emissions, amplitude fully compatible for proper
interoperability.
s Programmable scrambler seed for better FCC
compliancy.
s IEEE 802.3u Clause 28 compliant autonegotiation
for full 10 Mbits/s and 100 Mbits/s control.
s Extended management support with interrupt
capabilities.
s PHY MIB support.
s Low-power 500 mA max.
— Low-cost 128-pin SQFP packaging with heat
spreader.
1. ISO is a registered trademark of The International Organization
of Standardization.
2. IEC is a registered trademark of The International Electrotechni-
cal Commission.
3. EIA is a registered trademark of Electronic Industries Associa-
tion.
4. ANSI is a registered trademark of American National Standards
Institute, Inc.
5. IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
1 page  
Preliminary Data Sheet
July 2000
Pin Information
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
RXVDD0
RX+_0
RX–_0
RXGND0
REF100_0
TX+_0
TX–_0
TXVDD0
TXVDD1
TX–_1
TX+_1
REF100_1
RXGND1
RX–_1
RX+_1
RXVDD1
REFGND
CSVDD10
CSGND10
CSGND100
CSVDD100
REF10
RXVDD2
RX+_2
RX–_2
RXGND2
REF100_2
TX+_2
TX–_2
TXVDD2
TXVDD3
TX–_3
TX+_3
REF100_3
RXGND3
RX–_3
RX+_3
RXVDD3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
LU3X34FTR
102 RMII_RXER_0
101 CRS_DV_0
100 FD100_0/COL_0
99 TXEN_1
98 RMII_TXD_1[0]
97 RMII_TXD_1[1]
96 RMII_RXD_1[0]
95 RMII_RXD_1[1]
94 CRS_DV_1/PHYAD[2]
93 FD100_1/COL_1
92 DIGVDD1
91 DIGGND1
90 RMII_RXER_1
89 IOVDD3
88 IOGND3
87 RESERVED
86 RMII_RXER_2
85 FD10_3
84 DIGVDD2
83 DIGGND2
82 FD10_2
81 FD10_1
80 FD10_0
79 FD100_2/COL_2
78 CRS_DV_2/PHYAD[3]
77 RMII_RXD_2[1]
76 RMII_RXD_2[0]
75 RMII_TXD_2[1]
74 RMII_TXD_2[0]
73 TXEN_2
72 IOVDD4
71 IOGND4
70 RESERVED
69 RMII_RXER_3
68 FD100_3/COL_3
67 CRS_DV_3/PHYAD[4]
66 IOVDD5
65 RESERVED
Figure 2. Pin Diagram (RMII Mode)
Lucent Technologies Inc.
5-7511(F).c.r7
5
5 Page 
Preliminary Data Sheet
July 2000
LU3X34FTR
Quad 3 V 10/100 Ethernet Transceiver TX/FX
Pin Descriptions (continued)
Table 6. LED/Configuration Pins (continued)
Pin No.
116, 122, 44,
50
Pin Name
LEDFD_[0:3]/
HD10_[0:3]/
SD–[0:3]
I/O
I/O↑
117, 123, 45,
51
LEDCOL_ [0:3]/
HD100_[0:3]
I/O↑
40 PAUSE I
Table 7. Special Mode Configurations
Pin No.
118, 124, 46,
52
Pin Name*
LEDLNK_ [0:3]/
FOSEL _[0:3]
I/O
I/O↓
39
INTZ
O
125 TESTMSEL
I
42 ISOLATE I
128, 87, 70,
65
RESERVED
—
* Smaller font indicates that the pin has multiple functions.
Pin Description
Full-Duplex LED Output. Indicates full duplex for
ports 0—3.
10 Mbits/s Half-Duplex Operation. If FOSEL is low
during powerup or reset, these are input pins that
configure ports 0—3 for 10 Mbits/s half-duplex oper-
ation and sets register 4, bit 5 (see Figure 12). When
autonegotiation is disabled, it sets register 0, bit 13,
the speed bit, to 0 and bit 8, the duplex mode bit, to
0. If fiber mode is selected, bit 5, register 4h will be
set to 0.
Signal Detect –. In fiber mode, these pins are the
negative signal detect input from the fiber module.
These pins have an internal 40 kΩ pull-up resistor.
Activity LED Outputs. These pins indicate collision
status of ports 0—3, respectively.
100 Mbit/s Half-Duplex Operation. During powerup
or reset, these are input pins to configure ports 0—3
for 100 Mbits/s half-duplex operation and sets regis-
ter 4, bit 7 (see Figure 12). If autonegotiation is dis-
abled, it sets bit 13 in register 0 to 1. These pins
have an internal 40 kΩ pull-up resistor.
Pause. The logic level of this pin is latched into reg-
ister 4, bit 10 for all four ports during powerup or
reset. It is used to inform the autonegotiation link
partner that the MAC sublayer has pause/flow con-
trol capability when set in full-duplex mode. This
must not be set to 1 unless FD is also set.
Pin Description
Link LED Output. Each of these LEDs turns on
when there is a good link and blinks when there is
activity.
Fiber-Optic Select. These are input pins during
powerup and reset to configure ports 0—3 into fiber-
optic mode (see Figure 12). These pins have an
internal 40 kΩ pull-down resistor.
Interrupt. Open drain only pin.
Test Mode Select. This pin should be tied low.
Isolate. If this pin is high, all MII inputs are ignored
and all MII outputs are 3-stated.
Reserved. These are a reserved pins and should be
left floating.
Lucent Technologies Inc.
11
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