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PDF LTC1550 Data sheet ( Hoja de datos )

Número de pieza LTC1550
Descripción Low Noise/ Switched Capacitor Regulated Voltage Inverters
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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LTC1550/LTC1551
Low Noise, Switched
Capacitor Regulated
Voltage Inverters
FEATURES
s Regulated Negative Voltage from a Single
Positive Supply
s Low Output Ripple: Less Than 1mVP-P Typ
s High Charge Pump Frequency: 900kHz Typ
s Small Charge Pump Capacitors: 0.1µF
s Requires Only Four External Capacitors
s Fixed – 4.1V or Adjustable Output
s Shutdown Mode Drops Supply Current to < 1µA
s High Output Current: Up to 10mA, VCC = 5V
s Output Regulation: 5%
s Available in SO-8 and 16-Lead SSOP
U
APPLICATIONS
s GaAs FET Bias Generators
s Negative Supply Generators
s Battery-Powered Systems
s Single Supply Applications
, LTC and LT are registered trademarks of Linear Technology Corporation.
DESCRIPTION
The LTC®1550/LTC1551 are switched capacitor charge
pump voltage inverters which include internal linear post-
regulators to minimize output ripple. Output voltages are
fixed at – 4.1V, with ripple voltages typically below 1mVP-P.
The LTC1550 is also available in an adjustable output
voltage version. The LTC1550/LTC1551 are ideal for use
as bias voltage generators for GaAs transmitter FETs in
portable RF and cellular telephone applications.
The LTC1550/LTC1551 operate from single 4.5V to 6.5V
supplies and draw typical quiescent currents of 4.25mA
with a 5V supply. Each device includes a TTL compatible
Shutdown pin which drops supply current to 0.2µA typi-
cally. The LTC1550 Shutdown pin is active low (SHDN),
while the LTC1551 Shutdown pin is active high (SHDN).
Only four external components are required: an input bypass
capacitor, two 0.1µF charge pump capacitors and a filter
capacitoratthelinearregulatoroutput.TheadjustableLTC1550
requires two additional resistors to set the output voltage. The
LTC1550/LTC1551 will supply up to 10mA output current
with a 5V supply, while maintaining guaranteed output
regulation of ±5%.
The fixed voltage LTC1550/LTC1551 are available in S0-8
plastic packages. The adjustable LTC1550 is available in a
16-pin SSOP.
TYPICAL APPLICATION
VCC
+ 4.7µF
CIN
– 4.1V Generator with 1mVP-P Noise
1
SHDN
2
VCC
SENSE
CPOUT
8
7
LTC1551
3 C1+
GND 6
4
VOUT
C15
C1
0.1µF
CCP
0.1µF
FERRITE BEAD
COUT
10µF
VOUT = –4.1V
ILOAD = 5mA
CL
0.1µF
1550/51 F01
VOUT Output Noise and Ripple
VOUT
AC COUPLED
2mV/DIV
10µs/DIV
1550/51 TA02
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LTC1550 pdf
LTC1550/LTC1551
TYPICAL PERFORMANCE CHARACTERISTICS
Spot Noise
(See Figure 2, COUT = 10µF)
10
VCC = 5V
IL = 5mA
CIN = 4.7µF
COUT = 10µF
1 CL = 0.1µF
0.1
0.01
1
10
FREQUENCY (kHz)
100
LTC1550/51 • G12
Output Spectrum
(See Figure 2, COUT = 22µF)
90
80
VCC = 5V
IL = 5mA
70 CIN 4.7µF
COUT = 22µF
60 CL = 0.1µF
50
40
30
20
10
0
–10
100k
1M
FREQUENCY (Hz)
10M
LT1550/51 • G13
Spot Noise
(See Figure 2, COUT = 22µF)
10
VCC = 5V
IL = 5mA
CIN = 4.7µF
COUT = 22µF
1 CL = 0.1µF
0.1
0.01
1
10
FREQUENCY (kHz)
100
LTC1550/51 • G14
PIN FUNCTIONS
SHDN: Shutdown (TTL Compatible). This pin is active low
(SHDN) for the LTC1550 and active high (SHDN) for the
LTC1551. When this pin is at VCC (GND for LTC1551), the
LTC1550 operates normally. When SHDN is pulled low
(high for LTC1551), the LTC1550 enters shutdown mode.
In shutdown, the charge pump stops, the output collapses
to 0V, and the quiescent current drops typically to 0.2µA.
VCC: Power Supply. VCC requires an input voltage between
4.5V and 6.5V for the fixed voltage LTC1550CS8-4.1/
LTC1551CS8-4.1. The adjustable voltage LTC1550CGN/
LTC1550IGN operates with a VCC range of 2.7V to 6.5V.
Output voltage and output load current conditions depend
on the VCC supply voltage. Consult the Electrical Charac-
teristics table and Typical Performance Characteristics for
guaranteed test points. The difference between the input
voltage and output should never be set to exceed 14V or
damage to the chip may occur. VCC must be bypassed to
PGND (GND for 8-pin packages) with at least a 0.1µF
capacitor placed in close proximity to the chip. A 4.7µF or
larger bypass capacitor is recommended to minimize
noise and ripple at the output.
C1+: C1 Positive Input. Connect a 0.1µF capacitor between
C1+ and C1.
VOUT: Negative Voltage Output. This pin must be bypassed
to ground with a 4.7µF or larger capacitor to ensure
regulator loop stability. At least 10µF is recommended to
provide specified output ripple. An additional 0.1µF low
ESR capacitor is recommended to minimize high fre-
quency spikes at the output.
C1: C1 Negative Input. Connect a 0.1µF capacitor from
C1+ to C1.
GND: Ground. Connect to a low impedance ground. A
ground plane will help minimize regulation errors.
CPOUT: Negative Charge Pump Output. This pin requires a
0.1µF storage capacitor to ground.
SENSE: Connect to VOUT. The LTC1550/LTC1551 internal
regulator uses this pin to sense the output voltage. For
optimum regulation, SENSE should be connected close to
the output load.
SSOP PACKAGE ONLY
PGND: Power Ground. Connect to a low impedance ground.
PGND should be connected to the same potential as
AGND.
AGND: Analog Ground. Connect to a low impedance
ground. AGND should be connected to a ground plane to
minimize regulation errors.
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LTC1550 arduino
LTC1550/LTC1551
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8 765
0.228 – 0.244
(5.791 – 6.197)
0.150 – 0.157**
(3.810 – 3.988)
0.010
(0.254
0.020
0.508)
×
45°
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1 2 34
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.014 – 0.019
(0.355 – 0.483)
0.050
(1.270)
TYP
SO8 0996
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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